A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. - Takao Watanabe; Ryo Fujita; Kazumasa Yanagisawa; Hitoshi Tanaka; Kazushige Ayukawa; Mitsuru Soga; Yuji Tanaka; Yoshimitsu Sugie; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1997)