Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. - Yoshimitsu Yanagawa; Luong Dinh Hung; Chitaka Iwama; Niko Demus Barli; Shuichi Sakai; Hidehiko Tanaka (HiPC, 2003)

0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays. - Akira Kotabe; Yoshimitsu Yanagawa; Satoru Akiyama; Tomonori Sekiguchi (IEEE J. Solid State Circuits, 2010)

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. - Tomonori Sekiguchi; Kazuo Ono; Akira Kotabe; Yoshimitsu Yanagawa (IEEE J. Solid State Circuits, 2011)

Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. - Yoshimitsu Yanagawa; Kazuo Ono; Akira Kotabe; Riichiro Takemura; Tatsuo Nakagawa; Tomio Iwasaki; Takayuki Kawahara (ISCAS, 2012)

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. - Akira Kotabe; Riichiro Takemura; Yoshimitsu Yanagawa; Tomonori Sekiguchi; Kiyoo Itoh 001 (IEICE Trans. Electron., 2012)

Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. - Kazuo Ono; Yoshimitsu Yanagawa; Akira Kotabe; Riichiro Takemura; Tatsuo Nakagawa; Tomio Iwasaki; Takayuki Kawahara (IEICE Trans. Electron., 2012)

On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer. - Yoshimitsu Yanagawa; Naoshi Itabashi; Sonoko Migitaka; Takahide Yokoi; Makiko Yoshida; Takayuki Kawahara (BioCAS, 2013)