Reduced Scan Shift: A New Testing Method for Sequential Circuit. - Yoshinobu Higami; Seiji Kajihara; Kozo Kinoshita (ITC, 1994)

Test sequence compaction by reduced scan shift and retiming. - Yoshinobu Higami; Seiji Kajihara; Kozo Kinoshita (Asian Test Symposium, 1995)

Partial scan design and test sequence generation based on reduced scan shift method. - Yoshinobu Higami; Seiji Kajihara; Kozo Kinoshita (J. Electron. Test., 1995)

Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. - Yoshinobu Higami; Seiji Kajihara; Kozo Kinoshita (Asian Test Symposium, 1996)

Design of partially parallel scan chain. - Yoshinobu Higami; Kozo Kinoshita (ED&TC, 1997)

Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. - Yoshinobu Higami; Kewal K. Saluja; Kozo Kinoshita (Asian Test Symposium, 1998)

Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (Asian Test Symposium, 1999)

Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. - Yoshinobu Higami; Kewal K. Saluja; Kozo Kinoshita (VLSI Design, 1999)

Fault models and test generation for IDDQ testing: embedded tutorial. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (ASP-DAC, 2000)

Test sequence compaction for sequential circuits with reset states. - Yoshinobu Higami; Yuzo Takamatsu; Kozo Kinoshita (Asian Test Symposium, 2000)

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. - Yoshinobu Higami; Yuzo Takamatsu; Kewal K. Saluja; Kozo Kinoshita (J. Electron. Test., 2000)

Static test compaction for IDDQ testing of bridging faults in sequential circuits. - Yoshinobu Higami; Kewal K. Saluja; Yuzo Takamatsu; Kozo Kinoshita (Syst. Comput. Jpn., 2000)

Test Generation for Double Stuck-at Faults. - Yoshinobu Higami; Naoko Takahashi; Yuzo Takamatsu (Asian Test Symposium, 2001)

Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. - Hiroshi Takahashi; Marong Phadoongsidhi; Yoshinobu Higami; Kewal K. Saluja; Yuzo Takamatsu (Asian Test Symposium, 2001)

A Method to Reduce Power Dissipation during Test for Sequential Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu (Asian Test Symposium, 2002)

Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu (DELTA, 2002)

A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu; Seiji Kajihara; Irith Pomeranz (ICCD, 2003)

Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. - Yoshinobu Higami; Seiji Kajihara; Shin-ya Kobayashi; Yuzo Takamatsu (Asian Test Symposium, 2004)

Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. - Yuichi Sato; Hiroshi Takahashi; Yoshinobu Higami; Yuzo Takamatsu (Asian Test Symposium, 2004)

Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. - Hiroshi Takahashi; Yukihiro Yamamoto; Yoshinobu Higami; Yuzo Takamatsu (Asian Test Symposium, 2004)

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2004)

Improvement of the processors operating ratio in task scheduling using the deadline method. - Koichi Kashiwagi; Yoshinobu Higami; Shin-ya Kobayashi (Enhanced Methods in Computer Security, Biometric and Artificial Intelligence Systems, 2005)

On the fault diagnosis in the presence of unknown fault models using pass/fail information. - T. Seiyama; Hiroshi Takahashi; Yoshinobu Higami; Kazuo Yamazaki; Yuzo Takamatsu (ISCAS (3), 2005)

Test cost reduction for logic circuits: Reduction of test data volume and test application time. - Yoshinobu Higami; Seiji Kajihara; Hideyuki Ichihara; Yuzo Takamatsu (Syst. Comput. Jpn., 2005)

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ASP-DAC, 2006)

Diagnosis of Transistor Shorts in Logic Test Environment. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Sin-ya Kobayashi; Yuzo Takamatsu (ATS, 2006)

Effective Post-BIST Fault Diagnosis for Multiple Faults. - Hiroshi Takahashi; Shuhei Kadoyama; Yoshinobu Higami; Yuzo Takamatsu; Koji Yamazaki; Takashi Aikyo; Yasuo Sato (DFT, 2006)

On Finding Don't Cares in Test Sequences for Sequential Circuits. - Yoshinobu Higami; Seiji Kajihara; Irith Pomeranz; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2006)

A Consideration of Processor Utilization on Multi-Processor System. - Koichi Kashiwagi; Yoshinobu Higami; Shin-ya Kobayashi (Advances in Information Processing and Protection, 2007)

Development of Concealing the Purpose of Processing for Programs in a Distributed Computing Environment. - Yuji Kinoshita; Koichi Kashiwagi; Yoshinobu Higami; Shin-ya Kobayashi (Advances in Information Processing and Protection, 2007)

Reliability of Node Information on Autonomous Load Distribution Method. - Michihiko Kudo; Koichi Kashiwagi; Yoshinobu Higami; Shin-ya Kobayashi (Advances in Information Processing and Protection, 2007)

Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ATS, 2007)

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Shuhei Kadoyama; Takashi Aikyo; Yuzo Takamatsu; Koji Yamazaki; Toshiyuki Tsutsumi; Hiroyuki Yotsuyanagi; Masaki Hashizume (ATS, 2007)

Timing-Aware Diagnosis for Small Delay Defects. - Takashi Aikyo; Hiroshi Takahashi; Yoshinobu Higami; Junichi Ootsu; Kyohei Ono; Yuzo Takamatsu (DFT, 2007)

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Toru Kikkawa; Takashi Aikyo; Yuzo Takamatsu; Hiroyuki Yotsuyanagi; Masaki Hashizume (DFT, 2007)

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Yuzo Takamatsu (VLSI Design, 2007)

Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (ATS, 2008)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2008)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Post-BIST Fault Diagnosis for Multiple Faults. - Hiroshi Takahashi; Yoshinobu Higami; Shuhei Kadoyama; Yuzo Takamatsu; Koji Yamazaki; Takashi Aikyo; Yasuo Sato (IEICE Trans. Inf. Syst., 2008)

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. - Yuzo Takamatsu; Hiroshi Takahashi; Yoshinobu Higami; Takashi Aikyo; Koji Yamazaki (IEICE Trans. Inf. Syst., 2008)

New Class of Tests for Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Yuzo Takamatsu; Koji Yamazaki; Toshiyuki Tsutsumi; Hiroyuki Yotsuyanagi; Masaki Hashizume (Asian Test Symposium, 2009)

Diagnostic test generation for transition faults using a stuck-at ATPG tool. - Yoshinobu Higami; Yosuke Kurose; Satoshi Ohno; Hironori Yamaoka; Hiroshi Takahashi; Yoshihiro Shimizu; Takashi Aikyo; Yuzo Takamatsu (ITC, 2009)

A Novel Approach for Improving the Quality of Open Fault Diagnosis. - Koji Yamazaki; Toshiyuki Tsutsumi; Hiroshi Takahashi; Yoshinobu Higami; Takashi Aikyo; Yuzo Takamatsu; Hiroyuki Yotsuyanagi; Masaki Hashizume (VLSI Design, 2009)

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. - Hiroyuki Yotsuyanagi; Masaki Hashizume; Toshiyuki Tsutsumi; Koji Yamazaki; Takashi Aikyo; Yoshinobu Higami; Hiroshi Takahashi; Yuzo Takamatsu (VLSI Design, 2009)

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Sin-ya Kobayashi; Yuzo Takamatsu (Inf. Media Technol., 2009)

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Shin-ya Kobayashi; Yuzo Takamatsu (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Dynamic Parallel Downloading with Network Coding in $ lambda$-Grid Networks. - Kouji Hirata; Khamisi Kalegele; Yoshinobu Higami; Shin-ya Kobayashi (J. Commun., 2010)

Replica Selection and Downloading based on Wavelength Availability in λ-grid Networks. - Kouji Hirata; Khamisi Kalegele; Yoshinobu Higami; Shin-ya Kobayashi (J. Commun., 2010)

Fault simulation and test generation for clock delay faults. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (ASP-DAC, 2011)

Test Pattern Selection for Defect-Aware Test. - Yoshinobu Higami; Hiroshi Furutani; Takao Sakai; Shuichi Kameyama; Hiroshi Takahashi (Asian Test Symposium, 2011)

On Detecting Transition Faults in the Presence of Clock Delay Faults. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (Asian Test Symposium, 2011)

Enhancement of Clock Delay Faults Testing. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (ETS, 2011)

Dynamic routing and wavelength assignment in multifiber WDM networks with sparse wavelength conversion. - Dewiani; Kouji Hirata; Yoshinobu Higami; Shin-ya Kobayashi (ICTC, 2012)

Diagnosis for Bridging Faults on Clock Lines. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (PRDC, 2012)

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool. - Yoshinobu Higami; Satoshi Ohno; Hironori Yamaoka; Hiroshi Takahashi; Yoshihiro Shimizu; Takashi Aikyo (IEICE Trans. Inf. Syst., 2012)

Dynamic Routing and Wavelength Assignment with Backward Reservation in Wavelength-routed Multifiber WDM Networks. - Dewiani; Kouji Hirata; Khamisi Kalegele; Yoshinobu Higami; Shin-ya Kobayashi (J. Networks, 2012)

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. - Koji Yamazaki; Toshiyuki Tsutsumi; Hiroshi Takahashi; Yoshinobu Higami; Hironobu Yotsuyanagi; Masaki Hashizume; Kewal K. Saluja (Asian Test Symposium, 2013)

Injecting speculation on ideal trajectories into a trip-based integer programming model for elevator operations. - Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (GCCE, 2013)

Intermittently Proving Dynamic Programming to Solve Infinite MDPs on GPUs. - Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (CANDAR, 2013)

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (IEICE Trans. Inf. Syst., 2013)

Sushi: A Lightweight Distributed Image Storage System for Mobile and Web Services. - Kamoliddin Mavlonov; Yoshinobu Higami; Shin-ya Kobayashi (ACS, 2014)

Decreasing computational times for solving static elevator operation problems by assuming maximum waiting times. - Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (GCCE, 2014)

Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. - Yoshinobu Higami; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (ISVLSI, 2014)

A call-based integer programming model for static elevator operation problems. - Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (SCIS&ISIS, 2014)

Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs. - Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (Int. J. Netw. Comput., 2014)

Giving formal roles to elevators for breaking symmetry in static elevator operation problems. - Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (GCCE, 2015)

Diagnosis of Delay Faults Considering Hazards. - Yoshinobu Higami; Senling Wang; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (ISVLSI, 2015)

Design and Implementation of Data Synchronization and Offline Capabilities in Native Mobile Apps. - Kamoliddin Mavlonov; Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (ACIIDS (2), 2016)

Evaluation of Influence Exerted by a Malicious Group's Various Aims in the External Grid. - Kosuke Yamaguchi; Tsutomu Inamoto; Keiichi Endo; Yoshinobu Higami; Shinya Kobayashi (ACS, 2016)

Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. - Senling Wang; Hanan T. Al-Awadhi; Soh Hamada; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Jun Matsushima (ATS, 2016)

Road-Map to Bridge Theoretical and Practical Approaches for Elevator Operations. - Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (IIAI-AAI, 2016)

Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. - Yoshinobu Higami; Senling Wang; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

Comparative Evaluation of Bluetooth and Wi-Fi Direct for Tablet-Oriented Educational Applications. - Keiichi Endo; Ayame Onoyama; Dai Okano; Yoshinobu Higami; Shin-ya Kobayashi (ACIIDS (1), 2017)

Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD). - Senling Wang; Yoshinobu Higami; Hiroshi Takahashi; Masayuki Sato; Mitsunori Katsu; Shoichi Sekiguchi (ATS, 2017)

Harnessing Fuzziness of the Pragmatic Rule-Design Without IF-THEN Rules. - Tsutomu Inamoto; Yoshinobu Higami (FSDM, 2017)

On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects. - Yuuya Ohama; Hiroyuki Yotsuyanagi; Masaki Hashizume; Yoshinobu Higami; Hiroshi Takahashi (ISCIT, 2017)

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. - Yoshinobu Higami; Senling Wang; Hiroshi Takahashi; Shin-ya Kobayashi; Kewal K. Saluja (IEICE Trans. Inf. Syst., 2017)

Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems. - Tsutomu Inamoto; Yoshinobu Higami; Shin-ya Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines. - Hiroyuki Yotsuyanagi; Kotaro Ise; Masaki Hashizume; Yoshinobu Higami; Hiroshi Takahashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. - Senling Wang; Tomoki Aono; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (ATS, 2018)

Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. - Senling Wang; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (ETS, 2018)

Automotive Functional Safety Assurance by POST with Sequential Observation. - Senling Wang; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Jun Matsushima (IEEE Des. Test, 2018)

Evaluation of educational applications in terms of communication delay between tablets with Bluetooth or Wi-Fi Direct. - Keiichi Endo; Gakuto Fujioka; Ayame Onoyama; Dai Okano; Yoshinobu Higami; Shinya Kobayashi (Vietnam. J. Comput. Sci., 2018)

Formulation of a Test Pattern Measure That Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis. - Tsutomu Inamoto; Yoshinobu Higami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. - Hanan T. Al-Awadhi; Tomoki Aono; Senling Wang; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (IEICE Trans. Inf. Syst., 2020)

Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation. - Tsutomu Inamoto; Tomoki Nishino; Senling Wang; Yoshinobu Higami; Hiroshi Takahashi (GCCE, 2022)

SASL-JTAG: A Light-Weight Dependable JTAG. - Senling Wang; Shaoqi Wei; Jun Ma; Hiroshi Kai; Yoshinobu Higami; Hiroshi Takahashi; Akihiro Shimizu; Xiaoqing Wen; Tianming Ni (DFT, 2023)

Test Point Insertion for Multi-Cycle Power-On Self-Test. - Senling Wang; Xihong Zhou; Yoshinobu Higami; Hiroshi Takahashi; Hiroyuki Iwata; Yoichi Maeda; Jun Matsushima (ACM Trans. Design Autom. Electr. Syst., 2023)

Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. - Senling Wang; Shaoqi Wei; Hisashi Okamoto; Tatusya Nishikawa; Hiroshi Kai; Yoshinobu Higami; Hiroyuki Yotsuyanagi; Ruijun Ma; Tianming Ni; Hiroshi Takahashi; Xiaoqing Wen (ITC-Asia, 2024)

Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device. - Xihong Zhou; Senling Wang; Yoshinobu Higami; Hiroshi Takahashi (IEICE Trans. Inf. Syst., 2024)