An experimental large-capacity semiconductor file memory using 16-levels/cell storage. - Masashi Horiguchi; Masakazu Aoki; Yoshinobu Nakagome; Shin'ichi Ikenaga; Katsuhiro Shimohigashi (IEEE J. Solid State Circuits, 1988)

New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier. - Masakazu Aoki; Shin'ichi Ikenaga; Yoshinobu Nakagome; Masashi Horiguchi; Yasushi Kawase; Yoshifumi Kawamoto; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1989)

An on-chip smart memory for a data-flow CPU. - Gregory A. Uvieghara; Yoshinobu Nakagome; Deog-Kyoon Jeong; David A. Hodges (IEEE J. Solid State Circuits, 1990)

An experimental 1.5-V 64-Mb DRAM. - Yoshinobu Nakagome; Hitoshi Tanaka; Kan Takeuchi; Eiji Kume; Yasushi Watanabe; Toru Kaga; Yoshifumi Kawamoto; Fumio Murai; Ryuichi Izawa; Digh Hisamoto; Teruaki Kisu; Takashi Nishida; et al. (IEEE J. Solid State Circuits, 1991)

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. - Yoshinobu Nakagome; Kiyoo Itoh 001; Kan Takeuchi; Eiji Kume; Hitoshi Tanaka; Masanori Isoda; Tatsunori Musha; Toru Kaga; Teruaki Kisu; Takashi Nishida; Yoshifumi Kawamoto; Masakazu Aoki (IEEE J. Solid State Circuits, 1991)

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Yoshinobu Nakagome; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1991)

An experimental single-chip data flow CPU. - Gregory A. Uvieghara; Wen-mei W. Hwu; Yoshinobu Nakagome; Deog-Kyoon Jeong; David D. Lee; David A. Hodges; Yale N. Patt (IEEE J. Solid State Circuits, 1992)

Sub-1-V swing internal bus architecture for future low-power ULSIs. - Yoshinobu Nakagome; Kiyoo Itoh 001; Masanori Isoda; Kan Takeuchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. - Makoto Suzuki; Norio Ohkubo; Toshinobu Shinbo; Toshiaki Yamanaka; Akihiro Shimizu; Katsuro Sasaki; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1993)

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. - Hitoshi Tanaka; Yoshinobu Nakagome; Jun Etoh; Eiji Yamasaki; Masakazu Aoki; Kazuyuki Miyazawa (IEEE J. Solid State Circuits, 1994)

Trends in low-power RAM circuit technologies. - Kiyoo Itoh 001; Katsuro Sasaki; Yoshinobu Nakagome (Proc. IEEE, 1995)

A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. - Norio Ohkubo; Makoto Suzuki; Toshinobu Shinbo; Toshiaki Yamanaka; Akihiro Shimizu; Katsuro Sasaki; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1995)

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. - Suguru Tachibana; Hisayuki Higuchi; Koichi Takasugi; Katsuro Sasaki; Toshiaki Yamanaka; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1995)

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. - Takeshi Sakata; Masashi Horiguchi; Tomonori Sekiguchi; Shigeki Ueda; Hitoshi Tanaka; Eiji Yamasaki; Yoshinobu Nakagome; Masakazu Aoki; Toru Kaga; Makoto Ohkura; Ryo Nagai; Fumio Murai; et al. (IEEE J. Solid State Circuits, 1995)

Low-noise, high-speed data transmission using a ringing-canceling output buffer. - Tomonori Sekiguchi; Masashi Horiguchi; Takeshi Sakata; Yoshinobu Nakagome; Shigeki Ueda; Masakazu Aoki (IEEE J. Solid State Circuits, 1995)

Limitations and challenges of multigigabit DRAM chip design. - Kiyoo Itoh 001; Yoshinobu Nakagome; Shin'ichiro Kimura; Takao Watanabe (IEEE J. Solid State Circuits, 1997)

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. - Takao Watanabe; Ryo Fujita; Kazumasa Yanagisawa; Hitoshi Tanaka; Kazushige Ayukawa; Mitsuru Soga; Yuji Tanaka; Yoshimitsu Sugie; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1997)

A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. - Takashi Sato 001; Yoji Nishio; Toshio Sugano; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1999)

Review and future prospects of low-voltage RAM circuits. - Yoshinobu Nakagome; Masashi Horiguchi; Takayuki Kawahara; Kiyoo Itoh 001 (IBM J. Res. Dev., 2003)

Guest Editorial. - Shekhar Borkar; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 2003)

Introduction to the Special Issue. - Yoshinobu Nakagome; Bruce Gieseke (IEEE J. Solid State Circuits, 2004)