An 11Gb/s Inductive-Coupling Link with Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2008)

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2009)

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. - Shotaro Saito; Yoshinori Kohama; Yasufumi Sugimori; Yohei Hasegawa; Hiroki Matsutani; Toru Sano; Kazutaka Kasuga; Yoichi Yoshida; Kiichi Niitsu; Noriyuki Miura; Tadahiro Kuroda; Hideharu Amano (FPL, 2009)

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. - Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Makoto Saen; Shigenobu Komatsu; Kenichi Osada; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (ISSCC, 2009)

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. - Yasufumi Sugimori; Yoshinori Kohama; Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2009)

A High-Speed Inductive-Coupling Link With Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2009)

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. - Makoto Saen; Kenichi Osada; Yasuyuki Okuma; Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yoshinori Kohama; Yasufumi Sugimori; Kazutaka Kasuga; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yasufumi Sugimori; Yoshinori Kohama; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2011)