Test cost reduction by at-speed BISR for embedded DRAMs. - Yoshihiro Nagura; Michael Mullins; Anthony Sauvageau; Yoshinoro Fujiwara; Katsuya Furue; Ryuji Ohmura; Tatsunori Komoike; Takenori Okitaka; Tetsushi Tanizaki; Katsumi Dosaka; Kazutami Arimoto; Yukiyoshi Koda; et al. (ITC, 2001)