A 32-bank 256-Mb DRAM with cache and TAG. - Satoru Tanoi; Yasuhiro Tanaka; Tetsuya Tanabe; Akio Eta; Toshio Inada; Ryoji Hamazaki; Yoshio Ohtsuki; Masaru Uesugi (IEEE J. Solid State Circuits, 1994)

On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM. - Satoru Tanoi; Yasuhiro Tokunaga; Tetsuya Tanabe; Kazuhiko Takahashi; Atsuhiko Okada; Masahiro Itoh; Yoshiki Nagatomo; Yoshio Ohtsuki; Masaru Uesugi (IEEE J. Solid State Circuits, 1997)