A 64-Mb DRAM with meshed power line. - Toshio Yamada; Yoshiro Nakata; Junko Hasegawa; Noriaki Amano; Akinori Shibayama; Masaru Sasago; Naoto Matsuo; Toshiki Yabu; Susumu Matsumoto; Shozo Okada; Michihiro Inoue (IEEE J. Solid State Circuits, 1991)

Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. - Mutsuo Daito; Yoshiro Nakata; Satoshi Sasaki; Hiroyuki Gomyo; Hideki Kusamitsu; Yoshio Komoto; Kunihiko Iizuka; Katsuyuki Ikeuchi; Gil-Su Kim; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2011)