An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. - Hiroki Fujisawa; Shuichi Kubouchi; Koji Kuroki; Naohisa Nishioka; Yoshiro Riho; Hiromasa Noda; Isamu Fujii; Hideyuki Yoko; Ryuuji Takishita; Takahiro Ito; Hitoshi Tanaka; Masayuki Nakamura (ISSCC, 2006)

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. - Hiroki Fujisawa; Shuichi Kubouchi; Koji Kuroki; Naohisa Nishioka; Yoshiro Riho; Hiromasa Noda; Isamu Fujii; Hideyuki Yoko; Ryuuji Takishita; Takahiro Ito; Hitoshi Tanaka; Masayuki Nakamura (IEEE J. Solid State Circuits, 2007)

A new DRAM architecture and its control method for the system power consumption. - Yoshiro Riho; Kazuo Nakazato (ACM Great Lakes Symposium on VLSI, 2014)

A new extension method of retention time for memory cell on dynamic random access memory. - Yoshiro Riho; Kazuo Nakazato (Integr., 2014)

Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory. - Yoshiro Riho; Kazuo Nakazato (IEEE Trans. Very Large Scale Integr. Syst., 2014)