An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. - Shota Ishihara; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. - Shota Ishihara; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2010)

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. - Yoshiya Komatsu; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (ASP-DAC, 2011)

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. - Shota Ishihara; Ryoto Tsuchiya; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2011)

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design. - Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2013)