A Case for Low-Latency Network-on-Chip using Compression Routers. - Naoya Niwa; Yoshiya Shikama; Hideharu Amano; Michihiro Koibuchi (PDP, 2021)

Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. - Yoshiya Shikama; Ryuta Kawano; Hiroki Matsutani; Hideharu Amano; Yusuke Nagasaka; Naoto Fukumoto; Michihiro Koibuchi (PDP, 2021)

A Hardware Trojan Exploiting Coherence Protocol on NoCs. - Yoshiya Shikama; Michihiro Koibuchi; Hideharu Amano (PDCAT, 2022)

A traffic-aware memory-cube network using bypassing. - Yoshiya Shikama; Ryuta Kawano; Hiroki Matsutani; Hideharu Amano; Yusuke Nagasaka; Naoto Fukumoto; Michihiro Koibuchi (Microprocess. Microsystems, 2022)

A Compression Router for Low-Latency Network-on-Chip. - Naoya Niwa; Yoshiya Shikama; Hideharu Amano; Michihiro Koibuchi (IEICE Trans. Inf. Syst., 2023)