How to Make Robot a Robust and Interactive Communicator. - Yoshiyasu Ogasawara; Masashi Okamoto; Yukiko I. Nakano; Yong Xu 012; Toyoaki Nishida (KES (3), 2005)

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. - Yoshiyasu Ogasawara; Norito Kato; Masanori Yamato; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Mitaro Namiki; Hironori Nakajo (PDPTA, 2005)

Towards Reconfigurable Cache Memory for a Multithreaded Processor. - Yoshiyasu Ogasawara; Ippei Tate; Satoshi Watanabe; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)

A Model of Implementable SMT Processor on FPGA. - Ippei Tate; Yoshiyasu Ogasawara; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Satoshi Watanabe; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)

Toward Robots as Embodied Knowledge Media. - Toyoaki Nishida; Kazunori Terada; Takashi Tajima; Makoto Hatakeyama; Yoshiyasu Ogasawara; Yasuyuki Sumi; Yong Xu 012; Yasser F. O. Mohammad; Kateryna Tarasenko; Taku Ohya; Tatsuya Hiramatsu (IEICE Trans. Inf. Syst., 2006)

Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. - Satoshi Watanabe; Yoshiyasu Ogasawara; Ippei Tate; Hirofumi Yano; Hironori Nakajo (PDPTA, 2007)

A two-layered approach to communicative artifacts. - Yong Xu 012; Tatsuya Hiramatsu; Kateryna Tarasenko; Toyoaki Nishida; Yoshiyasu Ogasawara; Takashi Tajima; Makoto Hatakeyama; Masashi Okamoto; Yukiko I. Nakano (AI Soc., 2007)

Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. - Yoshiyasu Ogasawara; Pulung Waskito; Shinobu Miwa; Hironori Nakajo (CDES, 2009)

An Effective Replacement Strategy of Cache Memory for an SMT Processor. - Yoshiyasu Ogasawara; Hironori Nakajo (DSD, 2009)