Gate-level aged timing simulation methodology for hot-carrier reliability assurance. - Yoshiyuki Kawakami; Jingkun Fang; Hirokazu Yonezawa; Nobufusa Iwanishi; Lifeng Wu; Alvin I-Hsien Chen; Norio Koike; Ping Chen; Chune-Sin Yeh; Zhihong Liu (ASP-DAC, 2000)

GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design. - Lifeng Wu; Jingkun Fang; Heting Yan; Ping Chen; Alvin I-Hsien Chen; Yoshifumi Okamoto; Chune-Sin Yeh; Zhihong Liu; Nobufusa Iwanishi; Norio Koike; Hirokazu Yonezawa; Yoshiyuki Kawakami (ISQED, 2000)

Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. - Takashi Sato 001; Toshiki Kanamoto; Atsushi Kurokawa; Yoshiyuki Kawakami; Hiroki Oka; Tomoyasu Kitaura; Hiroyuki Kobayashi; Masanori Hashimoto (ASP-DAC, 2003)

A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop. - Yoshiyuki Kawakami; Makoto Terao; Masahiro Fukui; Shuji Tsukiyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Conformational Analyses and MO Studies of f152A1 and Its Analogues as Potent Protein Kinase Inhibitors. - Megumi Ikemori-Kawada; Takatoshi Kawai; Masaki Goto; Yuan John Wang; Yoshiyuki Kawakami (J. Chem. Inf. Model., 2009)

Docking Simulation Study and Kinase Selectivity of f152A1 and Its Analogs. - Megumi Ikemori-Kawada; Atsushi Inoue; Masaki Goto; Yuan John Wang; Yoshiyuki Kawakami (J. Chem. Inf. Model., 2012)