Heuristic Minimazation of Multiple-Valued Relations. - Yosinori Watanabe; Robert K. Brayton (ICCAD, 1991)

Incremental Synthesis for Engineering Changes. - Yosinori Watanabe; Robert K. Brayton (ICCD, 1991)

The maximum set of permissible behaviors for FSM networks. - Yosinori Watanabe; Robert K. Brayton (ICCAD, 1993)

Heuristic Minimization of Synchronous Relations. - Vigyan Singhal; Yosinori Watanabe; Robert K. Brayton (ICCD, 1993)

Logic Optimization with Multi-Output Gates. - Yosinori Watanabe; Lisa M. Guerra; Robert K. Brayton (ICCD, 1993)

Heuristic minimization of multiple-valued relations. - Yosinori Watanabe; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

State Minimization of Pseudo Non-Deterministic FSM's. - Yosinori Watanabe; Robert K. Brayton (EDAC-ETC-EUROASIC, 1994)

A delay model for logic synthesis of continuously-sized networks. - Joel Grodstein; Eric Lehman; Heather Harkness; Bill Grundmann; Yosinori Watanabe (ICCAD, 1995)

Permissible functions for multioutput components in combinational logic optimization. - Yosinori Watanabe; Lisa M. Guerra; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Logic decomposition during technology mapping. - Eric Lehman; Yosinori Watanabe; Joel Grodstein; Heather Harkness (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets. - Marco Sgroi; Luciano Lavagno; Yosinori Watanabe; Alberto L. Sangiovanni-Vincentelli (ICATPN, 1999)

Designing digital video systems: modeling and scheduling. - H. J. H. N. Kenter; Claudio Passerone; W. J. M. Smits; Yosinori Watanabe; Alberto L. Sangiovanni-Vincentelli (CODES, 1999)

Task generation and compile-time scheduling for mixed data-control embedded software. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Marc Massot; Sandra Moral; Claudio Passerone; Yosinori Watanabe; Alberto L. Sangiovanni-Vincentelli (DAC, 2000)

Area and search space control for technology mapping. - Dirk-Jan Jongeneel; Yosinori Watanabe; Robert K. Brayton; Ralph H. J. M. Otten (DAC, 2000)

Generation of minimal size code for scheduling graphs. - Claudio Passerone; Yosinori Watanabe; Luciano Lavagno (DATE, 2001)

Constraints specification at higher levels of abstraction. - Felice Balarin; Jerry R. Burch; Luciano Lavagno; Yosinori Watanabe; Roberto Passerone; Alberto L. Sangiovanni-Vincentelli (HLDVT, 2001)

Modeling and Designing Heterogeneous Systems. - Felice Balarin; Luciano Lavagno; Claudio Passerone; Alberto L. Sangiovanni-Vincentelli; Marco Sgroi; Yosinori Watanabe (Concurrency and Hardware Design, 2002)

Quasi-Static Scheduling of Independent Tasksfor Reactive Systems. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Claudio Passerone; Yosinori Watanabe (ICATPN, 2002)

Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. - Felice Balarin; Luciano Lavagno; Claudio Passerone; Alberto L. Sangiovanni-Vincentelli; Yosinori Watanabe; Guang Yang 004 (CODES, 2002)

False Path Elimination in Quasi-Static Scheduling. - G. Arrigoni; L. Duchini; Claudio Passerone; Luciano Lavagno; Yosinori Watanabe (DATE, 2002)

Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. - Felice Balarin; Luciano Lavagno; Claudio Passerone; Yosinori Watanabe (EMSOFT, 2002)

Formal verification of embedded system designs at multiple levels of abstraction. - Xi Chen 024; Fang Chen; Harry Hsieh; Felice Balarin; Yosinori Watanabe (HLDVT, 2002)

Simulation Trace Verification for Quantitative Constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (Embedded Software for SoC, 2003)

State Space Compression in History Driven Quasi-Static Scheduling. - Antonio G. Lomeña; Marisa López-Vallejo; Yosinori Watanabe; Alex Kondratyev (Embedded Software for SoC, 2003)

Case Studies of Model Checking for Embedded System Designs. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (ACSD, 2003)

Quasi-Static Scheduling for Concurrent Architectures. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Yosinori Watanabe (ACSD, 2003)

Temporofunctional crosstalk noise analysis. - Donald Chai; Alex Kondratyev; Yajun Ran; Kenneth H. Tseng; Yosinori Watanabe; Malgorzata Marek-Sadowska (DAC, 2003)

Automatic trace analysis for logic of constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (DAC, 2003)

Gain-based technology mapping for discrete-size cell libraries. - Bo Hu 006; Yosinori Watanabe; Alex Kondratyev; Malgorzata Marek-Sadowska (DAC, 2003)

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (DATE, 2003)

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. - Antonio G. Lomeña; Marisa Luisa López-Vallejo; Yosinori Watanabe; Alex Kondratyev (DATE, 2003)

Verifying LOC based functional and performance constraints. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (HLDVT, 2003)

Metropolis: An Integrated Electronic System Design Environment. - Felice Balarin; Yosinori Watanabe; Harry Hsieh; Luciano Lavagno; Claudio Passerone; Alberto L. Sangiovanni-Vincentelli (Computer, 2003)

Formal Verification for Embedded System Designs. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (Des. Autom. Embed. Syst., 2003)

A BMC-formulation for the scheduling problem in highly constrained hardware Systems. - Gianpiero Cabodi; Sergio Nocco; Stefano Quer; Alex Kondratyev; Luciano Lavagno; Yosinori Watanabe (BMC@CAV, 2003)

Eliminating False Positives in Crosstalk Noise Analysis. - Yajun Ran; Alex Kondratyev; Yosinori Watanabe; Malgorzata Marek-Sadowska (DATE, 2004)

Separation of concerns: overhead in modeling and efficient simulation techniques. - Guang Yang 004; Alberto L. Sangiovanni-Vincentelli; Yosinori Watanabe; Felice Balarin (EMSOFT, 2004)

Quasi-static Scheduling for Concurrent Architectures. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Alexander Taubin; Yosinori Watanabe (Fundam. Informaticae, 2004)

Logic of constraints: a quantitative performance and functional constraint formalism. - Xi Chen 024; Harry Hsieh; Felice Balarin; Yosinori Watanabe (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Simulation based deadlock analysis for system level designs. - Xi Chen 024; Abhijit Davare; Harry Hsieh; Alberto L. Sangiovanni-Vincentelli; Yosinori Watanabe (DAC, 2005)

A Time Slice Based Scheduler Model for System Level Design. - Luciano Lavagno; Claudio Passerone; Vishal Shah; Yosinori Watanabe (DATE, 2005)

A structural approach to quasi-static schedulability analysis of communicating concurrent programs. - Cong Liu 013; Alex Kondratyev; Yosinori Watanabe; Alberto L. Sangiovanni-Vincentelli (EMSOFT, 2005)

A BMC-based formulation for the scheduling problem of hardware systems. - Gianpiero Cabodi; Alex Kondratyev; Luciano Lavagno; Sergio Nocco; Stefano Quer; Yosinori Watanabe (Int. J. Softw. Tools Technol. Transf., 2005)

Quasi-static scheduling of independent tasks for reactive systems. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Claudio Passerone; Yosinori Watanabe (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Eliminating false positives in crosstalk noise analysis. - Yajun Ran; Alex Kondratyev; Kenneth H. Tseng; Yosinori Watanabe; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Quasi-Static Scheduling of Concurrent Specifications. - Luciano Lavagno; Claudio Passerone; Alex Kondratyev; Yosinori Watanabe (Embedded Systems Handbook, 2005)

Functional Model Exploration for Multimedia Applications via Algebraic Operators. - Shinjiro Kakita; Yosinori Watanabe; Douglas Densmore; Abhijit Davare; Alberto L. Sangiovanni-Vincentelli (ACSD, 2006)

Schedulability Analysis of Petri Nets Based on Structural Properties. - Cong Liu 013; Alex Kondratyev; Yosinori Watanabe; Jörg Desel; Alberto L. Sangiovanni-Vincentelli (Fundam. Informaticae, 2008)

Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs. - Yosinori Watanabe (ACSD, 2009)

Runtime deadlock analysis for system level design. - Eric Cheung; Xi Chen 024; Harry Hsieh; Abhijit Davare; Alberto L. Sangiovanni-Vincentelli; Yosinori Watanabe (Des. Autom. Embed. Syst., 2009)

Incremental high-level synthesis. - Luciano Lavagno; Alex Kondratyev; Yosinori Watanabe; Qiang Zhu 005; Mototsugu Fujii; Mitsuru Tatesawa; Noriyasu Nakayama (ASP-DAC, 2010)

Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques. - Gianpiero Cabodi; Luciano Lavagno; Marco Murciano; Alex Kondratyev; Yosinori Watanabe (ACM Trans. Design Autom. Electr. Syst., 2010)

Realistic performance-constrained pipelining in high-level synthesis. - Alex Kondratyev; Luciano Lavagno; Mike Meyer; Yosinori Watanabe (DATE, 2011)

Exploiting area/delay tradeoffs in high-level synthesis. - Alex Kondratyev; Luciano Lavagno; Mike Meyer; Yosinori Watanabe (DATE, 2012)

Clearing the clutter: Unified modeling and verification methodology for system level hardware design. - Yosinori Watanabe; Stuart Swan (MEMOCODE, 2012)

Share with care: a quantitative evaluation of sharing approaches in high-level synthesis. - Alex Kondratyev; Luciano Lavagno; Mike Meyer; Yosinori Watanabe (DATE, 2013)

Hardware/Software Codesign Across Many Cadence Technologies. - Grant Martin; Frank Schirrmeister; Yosinori Watanabe (Handbook of Hardware/Software Codesign, 2017)