Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. - Tetsuya Sueyoshi; Hiroshi Uchida; Hans Jürgen Mattausch; Tetsushi Koide; Yosuke Mitani; Tetsuo Hironaka (ASP-DAC, 2004)

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. - Kazuo Matsukawa; Takashi Morie; Yusuke Tokunaga; Shiro Sakiyama; Yosuke Mitani; Masao Takayama; Takuji Miki; Akinori Matsumoto; Koji Obata; Shiro Dosho (ASP-DAC, 2009)

A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver. - Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Koji Obata; Yusuke Tokunaga; Shiro Sakiyama; Shiro Dosho (CICC, 2010)

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator. - Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Koji Obata; Shiro Dosho; Akira Matsuzawa (IEEE J. Solid State Circuits, 2010)

A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method. - Kazuo Matsukawa; Koji Obata; Yosuke Mitani; Shiro Dosho (VLSIC, 2012)

A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver. - Koji Obata; Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Yusuke Tokunaga; Shiro Sakiyama; Shiro Dosho (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)