Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. - Kosuke Mizuno; Hiroki Noguchi; Guangji He; Yosuke Terachi; Tetsuya Kamino; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (FPL, 2010)

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. - Kosuke Mizuno; Hiroki Noguchi; Guangji He; Yosuke Terachi; Tetsuya Kamino; Tsuyoshi Fujinaga; Shintaro Izumi; Yasuo Ariki; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2011)

Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection. - Kosuke Mizuno; Yosuke Terachi; Kenta Takagi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (SiPS, 2012)

A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video. - Kosuke Mizuno; Kenta Takagi; Yosuke Terachi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2013)

An FPGA Implementation of a HOG-based Object Detection Processor. - Kosuke Mizuno; Yosuke Terachi; Kenta Takagi; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IPSJ Trans. Syst. LSI Des. Methodol., 2013)