A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. - I-Chyn Wey; Lung-Hao Chang; You-Gang Chen; Shih-Hung Chang; An-Yeu Wu (ISCAS (2), 2005)

Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. - Jhao-Ji Ye; You-Gang Chen; I-Chyn Wey; An-Yeu Wu (ISCAS, 2007)

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. - I-Chyn Wey; You-Gang Chen; An-Yeu Wu (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits. - I-Chyn Wey; You-Gang Chen; Changhong Yu; An-Yeu Wu; Jie Chen 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction. - You-Gang Chen; Hen-Wai Tsao; Chorng-Sii Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2013)