A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. - Shusuke Yoshimoto; Masaharu Terada; Youhei Umeki; Shunsuke Okumura; Atsushi Kawasumi; Toshikazu Suzuki; Shinichi Moriwaki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2012)

STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A negative-resistance sense amplifier for low-voltage operating STT-MRAM. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (ASP-DAC, 2015)

A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. - Tomoki Nakagawa; Shintaro Izumi; Koji Yanagida; Yuki Kitahara; Shusuke Yoshimoto; Yohei Umeki; Haruki Mori; Hiroto Kitahara; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; et al. (ISCAS, 2015)

A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. - Haruki Mori; Yohei Umeki; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2016)

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (IPSJ Trans. Syst. LSI Des. Methodol., 2016)