A 1.5-ns access time, 78- mu m2 memory-cell size, 64-kb ECL-CMOS SRAM. - Kunihiko Yamaguchi; Hiroaki Nambu; Kazuo Kanetani; Youji Idei; Noriyuki Homma; Toshiro Hiramoto; Nobuo Tamba; Kunihiko Watanabe; Masanori Odaka; Takahide Ikeda; Kenichi Ohhata; Yoshiaki Sakurai (IEEE J. Solid State Circuits, 1992)

High-speed sensing techniques for ultrahigh-speed SRAMs. - Hiroaki Nambu; Kazuo Kanetani; Youji Idei; Noriyuki Homma; Kunihiko Yamaguchi; Toshiro Hiramoto; Nobuo Tamba; Masanori Odaka; Kunihiko Watanabe; Takahide Ikeda; Kenichi Ohhata; Yoshiaki Sakurai (IEEE J. Solid State Circuits, 1992)

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. - Hiroalu Nambu; Kazuo Kanetani; Youji Idei; Tom Masuda; Keiichi Higeta; Masayuki Ohayashi; Masami Usami; Kunihiko Yamaguchi; Toshiyuki Kikuchi; Takahide Ikeda; Kenichi Ohhata; Takeshi Kusunoki; et al. (IEEE J. Solid State Circuits, 1995)

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. - Keiichi Higeta; Masami Usami; Masayuki Ohayashi; Yasuhiro Fujimura; Masahiko Nishiyama; Satoru Isomura; Kunihiko Yamaguchi; Youji Idei; Hiroaki Nambu; Kenichi Ohhata; Nadateru Hanta (IEEE J. Solid State Circuits, 1996)

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. - Youji Idei; Katsuhiro Shimohigashi; Masakazu Aoki; Hiromasa Noda; Hidetoshi Iwai; Katsuyuki Sato; Tadashi Tachibana (IEEE J. Solid State Circuits, 1998)