A detailed router based on simulated evolution. - Youn-Long Lin; Yu-Chin Hsu; Fur-Shing Tsai (ICCAD, 1988)

LES: a layout expert system. - Youn-Long Lin; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

An optimal transistor-chaining algorithm for CMOS cell layout. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (ICCAD, 1989)

A new integer linear programming formulation for the scheduling problem in data path synthesis. - Jiahn-Humg Lee; Yu-Chin Hsu; Youn-Long Lin (ICCAD, 1989)

Routing using a pyramid data structure. - Youn-Long Lin; Yu-Chin Hsu; Fur-Shing Tsai (ICCAD, 1989)

SILK: a simulated evolution router. - Youn-Long Lin; Yu-Chin Hsu; Fur-Shing Tsai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

LiB: A Cell Layout Generator. - Yung-Ching Hsieh; Chi-Yi Hwang; Youn-Long Lin; Yu-Chin Hsu (DAC, 1990)

Data Path Allocation Based on Bipartite Weighted Matching. - Chu-Yi Huang; Yen-Shen Chen; Youn-Long Lin; Yu-Chin Hsu (DAC, 1990)

Optimum and Heuristic Data Path Scheduling Under Resource Constraints. - Cheng-Tsung Hwang; Yu-Chin Hsu; Youn-Long Lin (DAC, 1990)

A new algorithm for tile generation. - Youn-Long Lin; Yu-Chin Hsu (Integr., 1990)

A fast transistor-chaining algorithm for CMOS cell layout. - Chi-Yi Hwang; Yung-Chin Hsieh; Youn-Long Lin; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Hybrid routing. - Youn-Long Lin; Yu-Chin Hsu; Fur-Shing Tsai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Scheduling for Functional Pipelining and Loop Winding. - Cheng-Tsung Hwang; Yu-Chin Hsu; Youn-Long Lin (DAC, 1991)

An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (DAC, 1991)

FLORA: A data path allocator based on branch-and-bound search. - Ta-Yung Liu; Youn-Long Lin (Integr., 1991)

Combining Logic Minimization and Folding for PLA's. - Yu-Chin Hsu; Youn-Long Lin; Hang-Ching Hsieh; Ting-Hai Chao (IEEE Trans. Computers, 1991)

LiB: a CMOS cell compiler. - Yung-Ching Hsieh; Chi-Yi Hwang; Youn-Long Lin; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Channel density reduction by routing over the cells. - Min-Siang Lin; Hourng-Wern Perng; Chi-Yi Hwang; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

An effective methodology for functional pipelining. - Tsing-Fa Lee; Allen C.-H. Wu; Daniel Gajski; Youn-Long Lin (ICCAD, 1992)

A Systolic Algorithm for the k-Nearest Neighbors Problem. - Yirng-An Chen; Youn-Long Lin; Long-Wen Chang (IEEE Trans. Computers, 1992)

Combining technology mapping and placement for delay-optimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (ICCAD, 1993)

PLS: a scheduler for pipeline synthesis. - Cheng-Tsung Hwang; Yu-Chin Hsu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. - Tsung-Yi Wu; Tzu-Chieh Tien; Allen C.-H. Wu; Youn-Long Lin (EDAC-ETC-EUROASIC, 1994)

State Assignment for Power and Area Minimization. - Kuo-Hua Wang; Wen-Sing Wang; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (ICCD, 1994)

Code generation for a DSP processor. - Wei-Kai Cheng; Youn-Long Lin (HLSS, 1994)

Performance-driven interconnection optimization for microarchitecture synthesis. - Yi-Min Jiang; Tsing-Fa Lee; TingTing Hwang; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A transformation-based method for loop folding. - Tsing-Fa Lee; Allen C.-H. Wu; Youn-Long Lin; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A Transformation-Based Approach for Storage Optimization. - Wei-Kai Cheng; Youn-Long Lin (DAC, 1995)

High-Level Synthesis -A Tutorial. - Allen C.-H. Wu; Youn-Long Lin (IEICE Trans. Inf. Syst., 1995)

TRACER-fpga: a router for RAM-based FPGA's. - Ching-Dong Chen; Yuh-Sheng Lee; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Combining technology mapping and placement for delay-minimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A row-based cell placement method that utilizes circuit structural properties. - Yu-Wen Tsay; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Storage optimization by replacing some flip-flops with latches. - Youn-Long Lin; Tsung-Yi Wu (EURO-DAC, 1996)

Register minimization beyond sharing among variables. - Tsung-Yi Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Computing brokerage and its application in VLSI design. - Youn-Long Lin (ASP-DAC, 1997)

Preserving HDL synthesis hierarchy for cell placement. - Yu-Wen Tsay; Wen-Jong Fang; Allen C.-H. Wu; Youn-Long Lin (ISPD, 1997)

A phase assignment method for virtual-wire-based hardware emulation. - Hsiao-Pin Su; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Recent developments in high-level synthesis. - Youn-Long Lin (ACM Trans. Design Autom. Electr. Syst., 1997)

A graph-partitioning-based approach for multi-layer constrained via minimization. - Yih-Chih Chou; Youn-Long Lin (ICCAD, 1998)

Integrating logic retiming and register placement. - Tzu-Chieh Tien; Hsiao-Pin Su; Yu-Wen Tsay; Yih-Chih Chou; Youn-Long Lin (ICCAD, 1998)

Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. - Hsiao-Pin Su; Allen C.-H. Wu; Youn-Long Lin (ISPD, 1998)

Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. - Wei-Kai Cheng; Youn-Long Lin (ISSS, 1998)

Layout-based Logic Decomposition for Timing Optimization. - Yun-Yin Lian; Youn-Long Lin (ASP-DAC, 1999)

A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. - Hsiao-Pin Su; Allen C.-H. Wu; Youn-Long Lin (DAC, 1999)

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. - Hsiao-Pin Su; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. - Wei-Kai Cheng; Youn-Long Lin (ACM Trans. Design Autom. Electr. Syst., 1999)

Array allocation taking into account SDRAM characteristics. - Hong-Kai Chang; Youn-Long Lin (ASP-DAC, 2000)

A VLSI implementation of the blowfish encryption/decryption algorithm. - Michael C.-J. Lin; Youn-Long Lin (ASP-DAC, 2000)

Performance-optimal clustering with retiming for sequential circuits. - Tzu-Chieh Tien; Youn-Long Lin (ASP-DAC, 2000)

A 3-step approach for performance-driven whole-chip routing. - Yih-Chih Chou; Youn-Long Lin (ASP-DAC, 2001)

A performance-driven standard-cell placer based on a modified force-directed algorithm. - Yih-Chih Chou; Youn-Long Lin (ISPD, 2001)

Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. - Hung-Pin Wen; Chien-Yu Lin; Youn-Long Lin (ISSS, 2001)

Test Scheduling and Test Access Architecture Optimization for System-on-Chip. - Huan-Shan Hsu; Jing-Reng Huang; Kuo-Liang Cheng; Chih-Wea Wang; Chih-Tsun Huang; Cheng-Wen Wu; Youn-Long Lin (Asian Test Symposium, 2002)

Test Scheduling of BISTed Memory Cores for SOC. - Chih-Wea Wang; Jing-Reng Huang; Yen-Fu Lin; Kuo-Liang Cheng; Chih-Tsun Huang; Cheng-Wen Wu; Youn-Long Lin (Asian Test Symposium, 2002)

Effective enforcement of path-delay constraints inperformance-driven placement. - Yih-Chih Chou; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard. - Tien-Wei Hsieh; Youn-Long Lin (ESTIMedia, 2004)

Integration, Verification and Layout of a Complex Multimedia SOC. - Chien-Liang Chen; Jiing-Yuan Lin; Youn-Long Lin (DATE, 2005)

A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. - Jian-Wen Chen; Cheng-Ru Chang; Youn-Long Lin (ISCAS (5), 2005)

An AMBA-compliant deblocking filter IP for H.264/AVC. - Sheng-Yu Shih; Cheng-Ru Chang; Youn-Long Lin (ISCAS (5), 2005)

A platform based SOC design methodology and its application in image compression. - Kai-Yuan Jan; Chih-Bin Fan; An-Chao Kuo; Wen-Chi Yen; Youn-Long Lin (Int. J. Embed. Syst., 2005)

A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. - Yu-Chien Kao; Huang-Chih Kuo; Yin-Tzu Lin; Chia-Wen Hou; Yi-Hsien Li; Hao-Tin Huang; Youn-Long Lin (APCCAS, 2006)

Introduction to H.264 advanced video coding. - Jian-Wen Chen; Chao-Yang Kao; Youn-Long Lin (ASP-DAC, 2006)

A near optimal deblocking filter for H.264 advanced video coding. - Shen-Yu Shih; Cheng-Ru Chang; Youn-Long Lin (ASP-DAC, 2006)

High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC. - Chao-Yang Kao; Huang-Chih Kuo; Youn-Long Lin (ICME, 2006)

A High-Performance Hardwired CABAC Decoder. - Jian-Wen Chen; Youn-Long Lin (ICASSP (2), 2007)

Reference frame access optimization for ultra high resolution H.264/AVC decoding. - Ping Chao; Youn-Long Lin (ICME, 2008)

A high-performance and memory-efficient architecture for H.264/AVC motion estimation. - Chao-Yang Kao; Youn-Long Lin (ICME, 2008)

An H.264/AVC full-mode intra-frame encoder for 1080HD video. - Huang-Chih Kuo; Youn-Long Lin (ICME, 2008)

A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. - Ping Chao; Youn-Long Lin (ISCAS, 2008)

A high-performance low-power H.264/AVC video decoder accelerator for embedded systems. - Huang-Chih Kuo; Jian-Wen Chen; Youn-Long Lin (ESTIMedia, 2009)

An effective dictionary-based display frame compressor. - Hui-Ting Yang; Jian-Wen Chen; Huang-Chih Kuo; Youn-Long Lin (ESTIMedia, 2009)

A High throughput CABAC Encoder for Ultra High Resolution Video. - Li-Cian Wu; Youn-Long Lin (ISCAS, 2009)

A high-performance hardwired CABAC decoder for ultra-high resolution video. - Jian-Wen Chen; Youn-Long Lin (IEEE Trans. Consumer Electron., 2009)

A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder. - Yuan-Chun Lin; Youn-Long Lin (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A 3D SoC design for H.264 application with on-chip DRAM stacking. - Tao Zhang 032; Kui Wang; Yi Feng 003; Yan Chen; Qun Li; Bing Shao; Jing Xie 006; Xiaodi Song; Lian Duan; Yuan Xie 001; Xu Cheng 001; Youn-Long Lin (3DIC, 2010)

A customized design of DRAM controller for on-chip 3D DRAM stacking. - Tao Zhang 032; Kui Wang; Yi Feng 003; Xiaodi Song; Lian Duan; Yuan Xie 001; Xu Cheng 001; Youn-Long Lin (CICC, 2010)

An elastic software cache with fast prefetching for motion compensation in video decoding. - Ping Chao; Youn-Long Lin (CODES+ISSS, 2010)

A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC main profile video. - Jian-Wen Chen; Li-Cian Wu; Po-Sheng Liu; Youn-Long Lin (IEEE Trans. Consumer Electron., 2010)

An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration. - Huan-Kai Peng; Youn-Long Lin (ACM Trans. Embed. Comput. Syst., 2010)

A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC. - Chao-Yang Kao; Youn-Long Lin (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation. - Chao-Yang Kao; Cheng-Long Wu; Youn-Long Lin (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A simple and effective lossless compression algorithm for video display frames. - Huang-Chih Kuo; Youn-Long Lin (ICME, 2011)

Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse. - Chia-Ming Hung; Youn-Long Lin (IET Comput. Digit. Tech., 2011)

A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video. - Huang-Chih Kuo; Li-Cian Wu; Hao-Ting Huang; Sheng-Tsung Hsu; Youn-Long Lin (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Hybrid Algorithm for Effective Lossless Compression of Video Display Frames. - Huang-Chih Kuo; Youn-Long Lin (IEEE Trans. Multim., 2012)

Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. - Wen-Tsuen Chen; Youn-Long Lin; Chen-Yi Lee; Jeng-Long Chiang; Meng-Fan Chang; Shih-Chieh Chang (IEEE Access, 2013)

VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding. - Huang-Chih Kuo; Youn-Long Lin (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

Power-Up Sequence Control for MTCMOS Designs. - Shi-Hao Chen; Youn-Long Lin; Mango Chia-Tso Chao (IEEE Trans. Very Large Scale Integr. Syst., 2013)

HarDNet: A Low Memory Traffic Network. - Ping Chao; Chao-Yang Kao; Yu-Shan Ruan; Chien-Hsiang Huang; Youn-Long Lin (ICCV, 2019)

RNNAccel: A Fusion Recurrent Neural Network Accelerator for Edge Intelligence. - Chao-Yang Kao; Huang-Chih Kuo; Jian-Wen Chen; Chiung-Liang Lin; Pin-Han Chen; Youn-Long Lin (CoRR, 2020)

HarDNet-BTS: A Harmonic Shortcut Network for Brain Tumor Segmentation. - Hung-Yu Wu; Youn-Long Lin (BrainLes@MICCAI (1), 2021)

Exploring the power of lightweight YOLOv4. - Chien-Yao Wang; Hong-Yuan Mark Liao; I-Hau Yeh; Yung-Yu Chuang; Youn-Long Lin (ICCVW, 2021)

HarDNet-MSEG: A Simple Encoder-Decoder Polyp Segmentation Neural Network that Achieves over 0.9 Mean Dice and 86 FPS. - Chien-Hsiang Huang; Hung-Yu Wu; Youn-Long Lin (CoRR, 2021)

SearchTrack: Multiple Object Tracking with Object-Customized Search and Motion-Aware Features. - Zhong-Min Tsai; Yu-Ju Tsai; Chien-Yao Wang; Hong-Yuan Mark Liao; Youn-Long Lin; Yung-Yu Chuang (BMVC, 2022)

HarDNet-DFUS: Enhancing Backbone and Decoder of HarDNet-MSEG for Diabetic Foot Ulcer Image Segmentation. - Ting-Yu Liao; Ching-Hui Yang; Yu-Wen Lo; Kuan-Ying Lai; Po-Huai Shen; Youn-Long Lin (DFUC@MICCAI, 2022)

HarDNet-DFUS: An Enhanced Harmonically-Connected Network for Diabetic Foot Ulcer Image Segmentation and Colonoscopy Polyp Segmentation. - Ting-Yu Liao; Ching-Hui Yang; Yu-Wen Lo; Kuan-Ying Lai; Po-Huai Shen; Youn-Long Lin (CoRR, 2022)

NeighborTrack: Improving Single Object Tracking by Bipartite Matching with Neighbor Tracklets. - Yu-Hsi Chen; Chien-Yao Wang; Cheng-Yun Yang; Hung-Shuo Chang; Youn-Long Lin; Yung-Yu Chuang; Hong-Yuan Mark Liao (CoRR, 2022)

NeighborTrack: Single Object Tracking by Bipartite Matching with Neighbor Tracklets and Its Applications to Sports. - Yu-Hsi Chen; Chien-Yao Wang; Cheng-Yun Yang; Hung-Shuo Chang; Youn-Long Lin; Yung-Yu Chuang; Hong-Yuan Mark Liao (CVPR Workshops, 2023)

Development and Applications of a Memory-Traffic-Efficient Convolutional Neural Network. - Youn-Long Lin (A-SSCC, 2024)