Fourier-based optimal design of a flexible manipulator path to reduce residual vibration of the endpoint. - Kyung-Jo Park; Youn-Sik Park (Robotica, 1993)

Residual Vibration Reduction of Time-Varying Flexible Structures by Input Shaping. - Kwanje Woo; Youn-Sik Park (J. Robotics Mechatronics, 1994)

Vibration reduction in flexible systems using a time-varying impulse sequence. - Jung-Keun Cho; Youn-Sik Park (Robotica, 1995)

Experimental evaluation of time-varying impulse shaping with a two-link flexible manipulator. - Jung-Keun Cho; Youn-Sik Park (Robotica, 1996)

Self-motion utilization for reducing vibration of a structurally flexible redundant robot manipulator system. - Seon-Jae Kim; Youn-Sik Park (Robotica, 1998)

Optimal input design for a cooperating robot to reduce vibration when carrying flexible objects. - Young-Chun Ji; Youn-Sik Park (Robotica, 2001)

Residual vibration reduction for a flexible structure using a modified input shaping technique. - Ki-Seong Lee; Youn-Sik Park (Robotica, 2002)

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion. - Youn-Sik Park; Sung-Wook Lee; Bai-Sun Kong; Kwang-Il Park; Jeong-Don Ihm; Joo-Sun Choi; Young-Hyun Jun (ISCAS, 2008)

Sound direction estimation using an artificial ear for robots. - Sungmok Hwang; Youngjin Park; Youn-Sik Park (Robotics Auton. Syst., 2011)

Robust H∞ Sliding Mode Descriptor Observer for Fault and Output Disturbance Estimation of Uncertain Systems. - Dong-Jae Lee; Youngjin Park; Youn-Sik Park (IEEE Trans. Autom. Control., 2012)

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM. - Yarui Peng; Bon Woong Ku; Youn-Sik Park; Kwang-Il Park; Seong-Jin Jang; Joo-Sun Choi; Sung Kyu Lim (DAC, 2015)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. - Chang-Kyo Lee; Yoon-Joo Eom; Jin-Hee Park; Junha Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jonghyuk Kim; Jong-Min Bang; Seungjun Shin; Hanna Park; et al. (ISSCC, 2017)

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (ISSCC, 2018)

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong-Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; et al. (IEEE J. Solid State Circuits, 2018)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Min-Su Ahn; Yong-Hun Kim; Yong Jae Lee; Dong-Seok Kang; Sung-Geun Do; Chang-Yong Lee; Gun-hee Cho; Jae-Koo Park; Jae-Sung Kim; et al. (IEEE J. Solid State Circuits, 2019)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)