A case for custom silicon in enabling low-cost information technology for developing regions. - Zhiyoong Foo; David Devescery; Thomas Schmid 002; Nathan Clark; R. Frank; Mohammad Hassan Ghaed; Ye-Sheng Kuo; Inhee Lee 001; Youn Sung Park; Zach Renner; Nathaniel Slottow; Vikas Vinay; et al. (ACM DEV, 2010)

Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. - Haoran Li; Youn Sung Park; Zhengya Zhang (FPGA, 2012)

High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. - Yaoyu Tao; Youn Sung Park; Zhengya Zhang (ISCAS, 2012)

A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM. - Youn Sung Park; David T. Blaauw; Dennis Sylvester; Zhengya Zhang (VLSIC, 2012)

A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. - Youn Sung Park; Yaoyu Tao; Zhengya Zhang (ISSCC, 2013)

A Low-Cost Audio Computer for Information Dissemination Among Illiterate People Groups. - Zhiyoong Foo; David Devescery; Mohammad Hassan Ghaed; Inhee Lee 001; Abishek Madhavan; Youn Sung Park; Aswin S. Rao; Zach Renner; Nathan Roberts; Aaron Schulman; Vikas Vinay; Michael Wieckowski; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. - Youn Sung Park; Yaoyu Tao; Shuanghong Sun; Zhengya Zhang (VLSIC, 2014)

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. - Youn Sung Park; David T. Blaauw; Dennis Sylvester; Zhengya Zhang (IEEE J. Solid State Circuits, 2014)

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. - Youn Sung Park; Yaoyu Tao; Zhengya Zhang (IEEE J. Solid State Circuits, 2015)

A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor. - David Garrett; Youn Sung Park; Seongjong Kim; Jay Sharma; Wenbin Huang; Majid Shaghaghi; Vinay Parthasarathy; Stephen Gibellini; Stephen Bailey; Mallik Moturi; Pieter Vorenkamp; Kurt Busch; et al. (ISSCC, 2023)