A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter. - Young-Deuk Jeon; Byeong-Lyeol Jeon; Seung-Chul Lee; Sang-Min Yoo; Seung-Hoon Lee 006 (ASP-DAC, 2000)

Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs. - Young-Deuk Jeon; Seung-Chul Lee; Sang-Min Yoo; Seung-Hoon Lee 006 (ISCAS, 2000)

A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications. - Young-Jae Cho; Doo-Hwan Sa; Yong-Woo Kim; Kyung-Hoon Lee; Hee-Cheol Choi; Seung-Hoon Lee 006; Young-Deuk Jeon; Seung-Chul Lee; Jong-Kee Kwon (CICC, 2006)

A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS. - Young-Deuk Jeon; Seung-Chul Lee; Kwi-Dong Kim; Jong-Kee Kwon; Jongdae Kim (ISSCC, 2007)

A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications. - Seung-Chul Lee; Young-Deuk Jeon; Kwi-Dong Kim; Jong-Kee Kwon; Jongdae Kim; Jeong-Woong Moon; Woo-Yol Lee (ISSCC, 2007)

A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications. - Seung-Chul Lee; Young-Deuk Jeon; Jong-Kee Kwon; Jongdae Kim (IEEE J. Solid State Circuits, 2007)

A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. - Jae-Won Nam; Young-Deuk Jeon; Young-Kyun Cho; Sang-Gug Lee 001; Jong-Kee Kwon (ESSCIRC, 2009)

A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS. - Young-Deuk Jeon; Young-Kyun Cho; Jae-Won Nam; Kwi-Dong Kim; Woo-Yol Lee; Kuk-Tae Hong; Jong-Kee Kwon (CICC, 2010)

A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. - Young-Kyun Cho; Young-Deuk Jeon; Jae-Won Nam; Jong-Kee Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS. - Jae-Won Nam; Young-Deuk Jeon; Seok-Ju Yun; Tae Moon Roh; Jong-Kee Kwon (ISOCC, 2011)

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications. - Young-Kyun Cho; Young-Deuk Jeon; Jae-Won Nam; Jong-Kee Kwon (Microelectron. J., 2011)

A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique. - Jae-Won Nam; Young-Deuk Jeon; Young-Kyun Cho; Jong-Kee Kwon (Microelectron. J., 2011)

A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture. - Young-Deuk Jeon; Jae-Won Nam; Kwi-Dong Kim; Tae Moon Roh; Jong-Kee Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Design of Analog and Digital Hybrid MAC Circuit for Artificial Neural Networks. - Ki-Hyuk Park; Min-Hyung Cho; Young-Deuk Jeon; Joo Hyun Lee (ICEIC, 2019)

Chiplet Heterogeneous-Integration AI Processor. - Youngsu Kwon; Jinho Han; Yong Cheol Peter Cho; Juyeob Kim; Jaehoon Chung; Jaewoong Choi; Sujin Park; Igyeong Kim; Hyunjeong Kwon; Jinkyu Kim; Hyunmi Kim; Won Jeon; et al. (ICEIC, 2023)

2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform. - Sujin Park; Yi-Gyeong Kim; Young-Deuk Jeon; Min-Hyung Cho; Jinho Han; Youngsu Kwon (ICEIC, 2023)

DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration. - Sujin Park; Young-Deuk Jeon; Yi-Gyeong Kim; Min-Hyung Cho; Jinho Han; Jaehoon Chung; Jaewoong Choi; Youngsu Kwon (ISOCC, 2023)

A 6.4Gb/s/pin HBM3 Digital PHY with Low-Power, Area-Efficient Techniques for Chiplet-Based AI processors in 12-nm CMOS. - Jaewoong Choi; Yi-Gyeong Kim; Juyeob Kim; Jaehoon Chung; Young-Deuk Jeon; Min-Hyung Cho; Sujin Park; Jinho Han (A-SSCC, 2024)