A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. - Yong-Cheol Bae; Joon-Young Park; Sang Jae Rhee; Seung-Bum Ko; Yonggwon Jeong; Kwang-Sook Noh; Young Hoon Son; Jaeyoun Youn; Yonggyu Chu; Hyunyoon Cho; Mijo Kim; Daesik Yim; et al. (ISSCC, 2012)

Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os. - Daniel W. Chang; Young Hoon Son; Jung Ho Ahn; Hoyoung Kim; Minwook Ahn; Michael J. Schulte; Nam Sung Kim (ICCAD, 2013)

Reducing memory access latency with asymmetric DRAM bank organizations. - Young Hoon Son; Seongil O; Yuhwan Ro; Jae W. Lee; Jung Ho Ahn (ISCA, 2013)

Scalable high-radix router microarchitecture using a network switch organization. - Jung Ho Ahn; Young Hoon Son; John Kim 001 (ACM Trans. Archit. Code Optim., 2013)

Row-buffer decoupling: A case for low-latency DRAM microarchitecture. - Seongil O; Young Hoon Son; Nam Sung Kim; Jung Ho Ahn (ISCA, 2014)

Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems. - Young Hoon Son; Seongil O; Hyunggyun Yang; Daejin Jung; Jung Ho Ahn; John Kim 001; Jangwoo Kim; Jae W. Lee (SC, 2014)

CiDRA: A cache-inspired DRAM resilience architecture. - Young Hoon Son; Sukhan Lee 002; Seongil O; Sanghyuk Kwon; Nam Sung Kim; Jung Ho Ahn (HPCA, 2015)

CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults. - Seongil O; Sanghyuk Kwon; Young Hoon Son; Yujin Park; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2015)

Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems. - Hadi Asghari Moghaddam; Young Hoon Son; Jung Ho Ahn; Nam Sung Kim (MICRO, 2016)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. - Sang-uhn Cha; Seongil O; Hyunsung Shin; Sangjoon Hwang; Kwang-Il Park; Seong-Jin Jang; Joo-Sun Choi; Gyo-Young Jin; Young Hoon Son; Hyunyoon Cho; Jung Ho Ahn; Nam Sung Kim (HPCA, 2017)

SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures. - Yuhwan Ro; Hyunyoon Cho; Eojin Lee; Daejin Jung; Young Hoon Son; Jung Ho Ahn; Jae W. Lee (HPCA, 2017)

Understanding power-performance relationship of energy-efficient modern DRAM devices. - Sukhan Lee 002; Yuhwan Ro; Young Hoon Son; Hyunyoon Cho; Nam Sung Kim; Jung Ho Ahn (IISWC, 2017)

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. - Young Hoon Son; Hyunyoon Cho; Yuhwan Ro; Jae W. Lee; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2017)

Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices. - Sukhan Lee 002; Hyunyoon Cho; Young Hoon Son; Yuhwan Ro; Nam Sung Kim; Jung Ho Ahn (IEEE Access, 2018)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)

GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State. - Seunghak Lee; Ki-Dong Kang; Hwanjun Lee; Hyungwon Park; Young Hoon Son; Nam Sung Kim; Daehoon Kim (MICRO, 2021)