A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. - Young-Hwa Kim; Jaewon Lee; SeongHwan Cho (ISCAS, 2010)

A time-domain flash ADC immune to voltage controlled delay line non-linearity. - Young-Hwa Kim; SeongHwan Cho (ASICON, 2011)

A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. - KwangSeok Kim; Young-Hwa Kim; Wonsik Yu; SeongHwan Cho (VLSIC, 2012)

A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. - KwangSeok Kim; Young-Hwa Kim; Wonsik Yu; SeongHwan Cho (IEEE J. Solid State Circuits, 2013)

A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC. - Jungho Kim; Young-Hwa Kim; KwangSeok Kim; Wonsik Yu; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source. - Young-Hwa Kim; SeongHwan Cho (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)

Acyclic Traffic Management in EtherCAT Networks: Novel Adaptive Grouping and Telegram Assignment Mechanism. - Danish Mehmood Mughal; Young-Hwa Kim; Byungchun Jeon; Sungwon Lee 001; Min Young Chung (IEEE Access, 2024)