An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation. - Young-Hyun Jun; Ki Jun; Song-Bai Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

High speed VLSI logic simulation using bitwise operations and parallel processing. - Young-Hyun Jun; Ibrahim N. Hajj; Sang-Heon Lee; Song-Bai Park (ICCD, 1990)

A New Colum Redundancy Scheme For Fast Access Time of 64-Mb DRAM. - Young-Hyun Jun; Weon-Hwa Jeong; Jong-Hoon Park; Tae-Hoon Kim; Seong-Wook Kim; Jae-Sik Lee; Seong-Jin Jang; Chang-Man Khang; Hee-Gook Lee (ISCAS, 1993)

Data-dependent evaluating latched CMOS differential logic family for statistical power reduction. - Bai-Sun Kong; Young-Hyun Jun (ISCAS, 2000)

Conditional-capture flip-flop for statistical power reduction. - Bai-Sun Kong; Sam-Soo Kim; Young-Hyun Jun (IEEE J. Solid State Circuits, 2001)

A high current driving charge pump with current regulation method. - Soon-Kyun Shin; Bai-Sun Kong; Chil-Gee Lee; Young-Hyun Jun; Jae-Whui Kim (CICC, 2005)

A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature. - Soon-Kyun Shin; Wang Yu; Bai-Sun Kong; Chil-Gee Lee; Young-Hyun Jun; Jae-Whui Kim (CICC, 2005)

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. - Sang-Bo Lee; Seong-Jin Jang; Jin-Seok Kwak; Sang-Jun Hwang; Young-Hyun Jun; Soo-In Cho; Chil-Gee Lee (IEEE J. Solid State Circuits, 2005)

Design of an Image Interpolator for Low Computation Complexity. - Young-Hyun Jun; Jong-Ho Yun; Jin-Sung Park; Myung-Ryul Choi (J. Inf. Process. Syst., 2006)

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (ISSCC, 2007)

A DLL with Jitter-Reduction Techniques for DRAM Interfaces. - Byung-Guk Kim; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Soo-In Cho (ISSCC, 2007)

CMOS Level Converter with Balanced Rise and Fall Delays. - Min-su Kim; Young-Hyun Jun; Sung-Bae Park; Bai-Sun Kong (IEICE Trans. Electron., 2007)

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control. - Chan-Kyung Kim; Jae-Goo Lee; Young-Hyun Jun; Chil-Gee Lee; Bai-Sun Kong (Microelectron. J., 2007)

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations. - Soon-Kyun Shin; Wang Yu; Young-Hyun Jun; Jae-Whui Kim; Bai-Sun Kong; Chil-Gee Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme. - Kwang-Il Oh; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Kinam Kim (CICC, 2008)

Presetting pulse-based flip-flop. - Chul Soo Kim; Joo-Seong Kim; Bai-Sun Kong; Yongsam Moon; Young-Hyun Jun (ISCAS, 2008)

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control. - Chan-Kyung Kim; Bai-Sun Kong; Chil-Gee Lee; Young-Hyun Jun (ISCAS, 2008)

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion. - Youn-Sik Park; Sung-Wook Lee; Bai-Sun Kong; Kwang-Il Park; Jeong-Don Ihm; Joo-Sun Choi; Young-Hyun Jun (ISCAS, 2008)

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. - Seung-Jun Bae; Young-Soo Sohn; Kwang-Il Park; Kyoung-Ho Kim; Dae-Hyun Chung; Jingook Kim; Si-Hong Kim; Min-Sang Park; Jae-Hyung Lee; Sam-Young Bang; Ho-Kyung Lee; In-Soo Park; et al. (ISSCC, 2008)

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. - Kyomin Sohn; Young-Ho Suh; Young-Jae Son; Daesik Yim; Kang-Young Kim; Dae-Gi Bae; Ted Kang; Hoon Lim; Soon-Moon Jung; Hyun-Geun Byun; Young-Hyun Jun; Kinam Kim (ISSCC, 2008)

Wafer-Level Characterization of Probecards using NAC Probing. - Gyu-Yeol Kim; Eon-Jo Byunb; Ki-Sang Kang; Young-Hyun Jun; Bai-Sun Kong (ITC, 2008)

A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface. - Sang Joon Hwang; Young-Hyun Jun; Man Young Sung (IEICE Electron. Express, 2008)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array. - Jung-Sik Kim; Kyung-Woo Nam; Chi Sung Oh; Han Gu Sohn; Donghyuk Lee; Sooyoung Kim; Jong-Wook Park; Yongjun Kim; Mi-Jo Kim; Jin-Guk Kim; Hocheol Lee; Jinhyoung Kwon; et al. (IEEE J. Solid State Circuits, 2008)

45nm Low-power Embedded Pseudo-SRAM with ECC-based Auto-adjusted Self-refresh Scheme. - Suk-Soo Pyo; Cheol-Ha Lee; Gyun-Hong Kim; Kyu-Myung Choi; Young-Hyun Jun; Bai-Sun Kong (ISCAS, 2009)

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. - Kyung-Soo Ha; Lee-Sup Kim; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Kinam Kim (ISSCC, 2009)

1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. - Yongsam Moon; Yong-Ho Cho; Hyun-Bae Lee; Byung-Hoon Jeong; Seok-Hun Hyun; Byungchul Kim; In-Chul Jeong; Seong-Young Seo; Junho Shin; Seok-Woo Choi; Ho-Sung Song; Jung-Hwan Choi; et al. (ISSCC, 2009)

New low-voltage small-area mixed-voltage I/O buffer. - Joung-Yeal Kim; Yoon-Suk Park; Young-Hyun Jun; Bai-Sun Kong (IEICE Electron. Express, 2009)

CMOS cross-coupled charge pump with improved latch-up immunity. - Su-Jin Park; Yonggu Kang; Joung-Yeal Kim; Tae Hee Han; Young-Hyun Jun; Chil-Gee Lee; Bai-Sun Kong (IEICE Electron. Express, 2009)

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN. - Kyung-Soo Ha; Lee-Sup Kim; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Kinam Kim (IEEE J. Solid State Circuits, 2009)

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces. - Byung-Guk Kim; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Soo-In Cho (IEEE J. Solid State Circuits, 2009)

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme. - Kwang-Il Oh; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Joo-Sun Choi; Kinam Kim (IEEE J. Solid State Circuits, 2009)

CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction. - Joung-Yeal Kim; Young-Hyun Jun; Bai-Sun Kong (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation. - Young-Won Kim; Joo-Seong Kim; Jae-Hyuk Oh; Yoon-Suk Park; Jong-Woo Kim; Kwang-Il Park; Bai-Sun Kong; Young-Hyun Jun (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

High-speed low-power bootstrapped level converter for dual supply systems. - Sang-Keun Han; KeeChan Park; Bai-Sun Kong; Young-Hyun Jun (APCCAS, 2010)

A temperature-stabilized voltage reference utilizing MOS body effect. - Haesick Sul; Young-Hyun Jun; Bai-Sun Kong (APCCAS, 2010)

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. - Jun-Hyun Bae; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Jae-Yoon Sim; Hong-June Park (CICC, 2010)

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors. - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (ESSCIRC, 2010)

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (ISSCC, 2010)

New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer. - Joung-Yeal Kim; Su-Jin Park; Yong-Ki Kim 002; Sang-Keun Han; Young-Hyun Jun; Chil-Gee Lee; Tae Hee Han; Bai-Sun Kong (IEICE Trans. Electron., 2010)

Low-Power High-Speed Data Serializer for Mobile TFT-LCD Driver ICs. - Jae-Hyuck Woo; Jae-Goo Lee; Young-Hyun Jun; Bai-Sun Kong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Dukha Park; Hoon Lee; Jin Ho Kim; Soon-Hong Ahn; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jae-Wook Lee 007; Han-Sung Joo; et al. (IEEE J. Solid State Circuits, 2010)

Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]. - Kwang-Il Oh; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Joo-Sun Choi; Kinam Kim (IEEE J. Solid State Circuits, 2010)

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. - Ki-Whan Song; Jinyoung Kim; Jae-Man Yoon; Sua Kim; Huijung Kim; Hyun-Woo Chung; Hyungi Kim; Kanguk Kim; Hwan-Wook Park; Hyun Chul Kang; Nam-Kyun Tak; Dukha Park; et al. (IEEE J. Solid State Circuits, 2010)

A line inversion-based stepwise data driving for low-power mobile TFT-LCDs. - Jae-Hyuck Woo; Jae-Goo Lee; Young-Hyun Jun; Bai-Sun Kong (IEEE Trans. Consumer Electron., 2010)

CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction. - Seung-Jae Choi; Young-Hyun Jun; Bai-Sun Kong (ASICON, 2011)

Line inversion-based mobile TFT-LCD driver IC with accurate quadruple-gamma-curve correction. - Jae-Hyuck Woo; Jae-Goo Lee; In-Suk Kim; Young-Hyun Jun; Gyoo-Cheol Hwang; Myung-Hee Lee; Bai-Sun Kong (A-SSCC, 2011)

Novel Low-Voltage Small-Area I/O Buffer for Mixed-Voltage Application. - Young-Wook Kim; Joung-Yeal Kim; Young-Hyun Jun; Bai-Sun Kong (FGIT-CA/CES3, 2011)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. - Hoeju Chung; Byung-Hoon Jeong; ByungJun Min; Youngdon Choi; Beak-Hyung Cho; Junho Shin; Jinyoung Kim; Jung Sunwoo; Joon-min Park; Qi Wang; Yong-jun Lee; Sooho Cha; et al. (ISSCC, 2011)

A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (ISSCC, 2011)

A study on accelerated built-in self test of multi-Gb/s high speed interfaces. - Seong-Won Kang; Jung-Hoon Chun; Young-Hyun Jun; Kee-Won Kwon (NESEA, 2011)

A Novel Body Bias Selection Scheme for Leakage Minimization. - Dong-Su Lee; Sung-Chan Kang; Young-Hyun Jun; Bai-Sun Kong (IEICE Trans. Electron., 2011)

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs. - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Satoru Yamada; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (IEICE Trans. Electron., 2011)

Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM. - Dong-Su Lee; Young-Hyun Jun; Bai-Sun Kong (IEEE J. Solid State Circuits, 2011)

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (IEEE J. Solid State Circuits, 2011)

A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity. - Seong-Young Seo; Jung-Hoon Chun; Young-Hyun Jun; Seok Kim; Kee-Won Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A low-power two-line inversion method for driving LCD panels. - Sung-Pil Choi; Gyoo-Cheol Hwang; Young-Hyun Jun; Kee-Won Kwon; Jung-Hoon Chun (ISCAS, 2012)

0.37mW/Gb/s low power SLVS transmitter for battery powered applications. - Youngkyun Jeong; Yoon-Chul Choi; Eun-Ji Choi; Seogheon Ham; Kee-Won Kwon; Young-Hyun Jun; Jung-Hoon Chun (ISCAS, 2012)

Adaptive frequency-controlled ultra-fast hysteretic buck converter for portable devices. - Kwang-Ho Kim; Bai-Sun Kong; Young-Hyun Jun (ISOCC, 2012)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory. - Seung-Hwan Shin; Dong-Kyo Shim; Jaeyong Jeong; Ohsuk Kwon; Sangyong Yoon; Myung-Hoon Choi; Tae-Young Kim; Hyun Wook Park; Hyun-Jun Yoon; Youngsun Song; Yoon-Hee Choi; Sang-Won Shim; et al. (VLSIC, 2012)

High-Speed Low-Power Boosted Level Converters for Dual Supply Systems. - Sang-Keun Han; KeeChan Park; Young-Hyun Jun; Bai-Sun Kong (IEICE Trans. Electron., 2012)

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (IEEE J. Solid State Circuits, 2012)

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface. - Chulbum Kim; Jinho Ryu; Tae-Sung Lee; Hyunggon Kim; Jaewoo Lim; Jaeyong Jeong; Seonghwan Seo; Hongsoo Jeon; Bokeun Kim; Inyoul Lee; Dooseop Lee; Pansuk Kwak; et al. (IEEE J. Solid State Circuits, 2012)

A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications. - June-Hee Lee; Sang-Hoon Kim; Young-Hyun Jun; Kee-Won Kwon; Jung-Hoon Chun (IEICE Electron. Express, 2013)

An all-digital PLL with supply insensitive digitally controlled oscillator. - Seong-Young Seo; Jung-Hoon Chun; Young-Hyun Jun; Kee-Won Kwon (IEICE Electron. Express, 2013)

Blind-oversampling adaptive oversample-level DFE receiver for unsynchronized global on-chip serial links. - Won-Hwa Shin; Young-Hyun Jun; Bai-Sun Kong (IEICE Electron. Express, 2013)

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH. - Yong-Sung Cho; Il-Han Park; Sangyong Yoon; Nam-Hee Lee; Sang-Hyun Joo; Ki-Whan Song; Kihwan Choi; Jin-Man Han; Kyehyun Kyung; Young-Hyun Jun (IEEE J. Solid State Circuits, 2013)

Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control. - Ji-Soo Chang; Hyoung-Seok Oh; Young-Hyun Jun; Bai-Sun Kong (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling. - Won-Hwa Shin; Young-Hyun Jun; Bai-Sun Kong (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Accurate quadruple-gamma-curve correction for line inversion-based mobile TFT-LCD driver ICS. - Jae-Hyuck Woo; Jae-Goo Lee; Young-Hyun Jun; Bai-Sun Kong (IEEE Trans. Consumer Electron., 2013)

A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL. - Kyoung-Ho Kim; Jun-Han Bae; Young-Hyun Jun; Kee-Won Kwon (IEICE Electron. Express, 2014)

CMOS Charge Pump With No Reversion Loss and Enhanced Drivability. - Joung-Yeal Kim; Su-Jin Park; Kee-Won Kwon; Bai-Sun Kong; Joo-Sun Choi; Young-Hyun Jun (IEEE Trans. Very Large Scale Integr. Syst., 2014)

10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface. - Hyun-Wook Lim; Sung-Won Choi; Sang-Kyu Lee; Chang-Hoon Baek; Jae-Youl Lee; Gyoo-Cheol Hwang; Bai-Sun Kong; Young-Hyun Jun (ISSCC, 2015)

A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface. - Hyun-Wook Lim; Sung-Won Choi; Jeong-Keun Ahn; Woong-Ki Min; Sang-Kyu Lee; Chang-Hoon Baek; Jae-Youl Lee; Gyoo-Cheol Hwang; Young-Hyun Jun; Bai-Sun Kong (IEEE J. Solid State Circuits, 2017)