A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. - Uk-Rae Cho; Tae-Hyoung Kim; Yong-Jin Yoon; Jong-Cheol Lee; Dae-Gi Bae; Nam-Seog Kim; Kang-Young Kim; Young-Jae Son; Jeong-Suk Yang; Kwon-Il Sohn; Sung-Tae Kim; In-Yeol Lee; et al. (IEEE J. Solid State Circuits, 2003)

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. - Kyomin Sohn; Young-Ho Suh; Young-Jae Son; Daesik Yim; Kang-Young Kim; Dae-Gi Bae; Ted Kang; Hoon Lim; Soon-Moon Jung; Hyun-Geun Byun; Young-Hyun Jun; Kinam Kim (ISSCC, 2008)