0.25-4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2015)

A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2015)

Time-mode techniques for fast-locking phase-locked loops. - Durand Jarrett-Amor; Young Jun Park 002; Fei Yuan 005 (ISCAS, 2016)

Time integrator for mixed-mode signal processing. - Young Jun Park 002; Durand Jarrett-Amor; Fei Yuan 005 (ISCAS, 2016)

Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2017)

1-1 MASH ΔΣ time-to-digital converter with differential cascode time integrator. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2017)

All-digital ΔΣ TDC with differential bi-directional gated-delay-line time integrator. - Young Jun Park 002; Fei Yuan 005 (MWSCAS, 2017)

Two-step pulse-shrinking time-to-digital converter. - Young Jun Park 002; Fei Yuan 005 (Microelectron. J., 2017)

All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator. - Young Jun Park 002; Parth Parekh; Fei Yuan 005 (Microelectron. J., 2018)