A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. - Dong-Uk Lee; Hyun-Woo Lee; Ki Chang Kwean; Young-Kyoung Choi; Hyong Uk Moon; Seung-Wook Kwack; Shin-Deok Kang; Kwan-Weon Kim; Yong Ju Kim; Young-Jung Choi; Patrick B. Moran; Jin-Hong Ahn; et al. (ISSCC, 2006)

A One-Cycle Lock Time Slew-Rate-Controlled Output Driver. - Young-Ho Kwak; Inhwa Jung; Hyung-Dong Lee; Young-Jung Choi; Yogendera Kumar; Chulwoo Kim (ISSCC, 2007)

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. - Dongsuk Shin; Janghoon Song; Hyunsoo Chae; Kwan-Weon Kim; Young-Jung Choi; Chulwoo Kim (ISSCC, 2007)

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. - Ki-Won Lee; Joo-Hwan Cho; Byoung-Jin Choi; Geun-Il Lee; Ho-Don Jung; Woo-Young Lee; Ki-Chon Park; Yongsuk Joo; Jaehoon Cha; Young-Jung Choi; Patrick B. Moran; Jin-Hong Ahn (IEEE J. Solid State Circuits, 2007)

A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. - Dongsuk Shin; Won-Joo Yun; Hyun-Woo Lee; Young-Jung Choi; Suki Kim; Chulwoo Kim (ESSCIRC, 2008)

SDTV Quality Assessment Using Energy Distribution of DCT Coefficients. - Young-Jung Choi; Ha-Joong Park; Xingang Liu; Kook-Yeol Yoo; Ho-Youl Jung (ICESS, 2008)

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. - Dong-Uk Lee; Shin-Deok Kang; Nak-Kyu Park; Hyun-Woo Lee; Young-Kyoung Choi; Jung-Woo Lee; Seung-Wook Kwack; Hyeong-Ouk Lee; Won-Joo Yun; Sang-Hoon Shin; Kwan-Weon Kim; Young-Jung Choi; et al. (ISSCC, 2008)

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. - Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Shin-Deok Kang; Ji-Yeon Yang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; Young-Ju Kim 001; Won-Jun Choi; Keun-Soo Song; Sang-Hoon Shin; et al. (ISSCC, 2008)

Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. - Jabeom Koo; Gil-Su Kim; Junyoung Song; Kwan-Weon Kim; Young-Jung Choi; Chulwoo Kim (CICC, 2009)

A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter. - Dongsuk Shin; Jabeom Koo; Won-Joo Yun; Young-Jung Choi; Chulwoo Kim (ISCAS, 2009)

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. - Hyun-Woo Lee; Won-Joo Yun; Young-Kyoung Choi; Hyang-Hwa Choi; Jong-Jin Lee; Ki-Han Kim; Shin-Deok Kang; Ji-Yeon Yang; Jae-Suck Kang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; et al. (ISSCC, 2009)

Coverage expandable current type code controlled DCC with TDC-based range selector. - Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Young-Jung Choi; Suki Kim (IEICE Electron. Express, 2009)

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. - Hyun-Woo Lee; Yong-Hoon Kim; Won-Joo Yun; Eun Young Park; Kang Youl Lee; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Kyung Whan Kim; Nam Gyu Rye; Kwan-Weon Kim; Jun Hyun Chun; et al. (ISCAS, 2010)

Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster. - Dongsuk Shin; Joo-Hwan Cho; Young-Jung Choi; Byong-Tae Chung (SoCC, 2010)

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. - Hyun-Woo Lee; Ki-Han Kim; Young-Kyoung Choi; Ju-Hwan Shon; Nak-Kyu Park; Kwan-Weon Kim; Chulwoo Kim; Young-Jung Choi; Byong-Tae Chung (ISSCC, 2011)

A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. - Hyun-Woo Lee; Soo-Bin Lim; Junyoung Song; Jabeom Koo; Dae-Han Kwon; Jong-Ho Kang; Yunsaing Kim; Young-Jung Choi; Kunwoo Park; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2012)

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. - Hyun-Woo Lee; Hoon Choi; Beom-Ju Shin; Kyung-Hoon Kim; Kyung Whan Kim; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Jae-Hwan Kim; Eun Young Park; Jong-Sam Kim; Jong-Hwan Kim; et al. (IEEE J. Solid State Circuits, 2012)

A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. - Hyun-Woo Lee; Ki-Han Kim; Young-Kyoung Choi; Ju-Hwan Sohn; Nak-Kyu Park; Kwan-Weon Kim; Chulwoo Kim; Young-Jung Choi; Byong-Tae Chung (IEEE J. Solid State Circuits, 2012)

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. - Junyoung Song; Hyun-Woo Lee; Soo-Bin Lim; Sewook Hwang; Yunsaing Kim; Young-Jung Choi; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2013)