A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (ISSCC, 2010)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (IEEE J. Solid State Circuits, 2011)

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. - Tae-Young Oh; Hoeju Chung; Jun-Young Park; Ki-Won Lee; Seung-Hoon Oh; Su-Yeon Doo; Hyoung-Joo Kim 002; ChangYong Lee; Hye-Ran Kim; Jong-Ho Lee; Jin-Il Lee; Kyung-Soo Ha; et al. (IEEE J. Solid State Circuits, 2015)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. - Chang-Kyo Lee; Yoon-Joo Eom; Jin-Hee Park; Junha Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jonghyuk Kim; Jong-Min Bang; Seungjun Shin; Hanna Park; et al. (ISSCC, 2017)

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong-Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; et al. (IEEE J. Solid State Circuits, 2018)