Analysis and modeling of a Low Voltage Triggered SCR ESD protection clamp with the very fast Transmission Line Pulse measurement. - Jae-Young Park; Jong-Kyu Song; Chang-Soo Jang; Young-Sang Son; Dae-Woo Kim (ISQED, 2010)

A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process. - Jae-Young Park; Dae-Woo Kim; Young-Sang Son; Jong-Kyu Song; Chang-Soo Jang; Won-Young Jung (IEICE Trans. Electron., 2011)

A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. - Young San Shin; Jae-Kyung Wee; Jong-Chan Ha; Ji-Hoon Lim; Yong-Ju Kim; Young-Sang Son (J. Circuits Syst. Comput., 2011)