A 1-Gb/s bidirectional I/O buffer using the current-mode scheme. - Jae-Yoon Sim; Young-Soo Sohn; Seung-Chan Heo; Hong-June Park; Soo-In Cho (IEEE J. Solid State Circuits, 1999)

A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. - Jae-Yoon Sim; Jang-Jin Nam; Young-Soo Sohn; Hong-June Park; Chang-Hyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2002)

A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation. - Young-Soo Sohn; Seung-Jun Bae; Hong-June Park; Changhyun Kim; Soo-In Cho (CICC, 2003)

A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme. - Seung-Jun Bae; Hyung-Joon Chi; Young-Soo Sohn; Hong-June Park (IEEE J. Solid State Circuits, 2005)

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. - Kyu-Hyoun Kim; Young-Soo Sohn; Chan-Kyoung Kim; Moon-Sook Park; Dong-Jin Lee; Woo-Seop Kim; Changhyun Kim (IEEE J. Solid State Circuits, 2006)

Field emission characteristics of an oxidized porous polysilicon field emitter using the electrochemical oxidation process. - Soon-Il Kwon; Sung-Won You; Young-Soo Sohn; Yong-Soo Cho 002; Byung-Nam Park; Sie-Young Choi (Microelectron. J., 2006)

Design and fabrication of a vibration sensor using a conductive ball. - Yong-Soo Cho 002; Sung-Wook Jang; Young-Soo Sohn; Sie-Young Choi (Microelectron. J., 2007)

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. - Seung-Jun Bae; Young-Soo Sohn; Kwang-Il Park; Kyoung-Ho Kim; Dae-Hyun Chung; Jingook Kim; Si-Hong Kim; Min-Sang Park; Jae-Hyung Lee; Sam-Young Bang; Ho-Kyung Lee; In-Soo Park; et al. (ISSCC, 2008)

A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling. - Seung-Jun Bae; Hyung-Joon Chi; Young-Soo Sohn; Jae-Seung Lee; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. - Jun-Hyun Bae; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Jae-Yoon Sim; Hong-June Park (CICC, 2010)

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (ISSCC, 2010)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface. - Hyung-Joon Chi; Jae-Seung Lee; Seong-Hwan Jeon; Seung-Jun Bae; Young-Soo Sohn; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2011)

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (IEEE J. Solid State Circuits, 2011)

An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits. - Il-Min Yi; Seung-Jun Bae; Young-Soo Sohn; Jae-Yoon Sim; Hong-June Park (ISOCC, 2012)

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. - Young-Sik Kim; Seon-Kyoo Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Bae Lee; Joo-Sun Choi; Hong-June Park; Jae-Yoon Sim (ISSCC, 2012)

A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. - Hye-Yoon Joo; Seung-Jun Bae; Young-Soo Sohn; Young-Sik Kim; Kyung-Soo Ha; Min-Su Ahn; Young-Ju Kim 001; Yong-Jun Kim; Ju-Hwan Kim; Won-Jun Choi; Chang-Ho Shin; Soo Hwan Kim; et al. (ISSCC, 2016)

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (ISSCC, 2016)

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. - Il-Min Yi; Seung-Jun Bae; Min-Kyun Chae; Soo-Min Lee; Young Jae Jang; Young-Chul Cho; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (VLSI Circuits, 2016)

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution. - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (IEEE J. Solid State Circuits, 2017)

An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM. - Joung-Wook Moon; Hye-Sung Yoo; Hundai Choi; Il-Won Park; Seok-Yong Kang; Jun-Bae Kim; Haeyoung Chung; Kiho Kim; Dong-Hun Lee; Ki-Jae Song; Seok-Hun Hyun; Indal Song; et al. (A-SSCC, 2018)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (ISSCC, 2018)

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. - Jin-Hyeok Baek; Chang-Kyo Lee; Kiho Kim; Daesik Moon; Gil-Hoon Cha; Jin-Seok Heo; Min-Su Ahn; Dong-Ju Kim; Jae-Joon Song; Seokhong Kwon; Jongmin Kim; Kyung-Soo Kim; et al. (VLSI Circuits, 2018)

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong-Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; et al. (IEEE J. Solid State Circuits, 2018)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. - Jin-Seok Heo; Kihan Kim; Dong-Hoon Lee; Chang-Kyo Lee; Daesik Moon; Kiho Kim; Jin-Hyeok Baek; Sung-Woo Yoon; Hui-Kap Yang; Kyungryun Kim; Youngjae Kim; Bokgue Park; et al. (VLSI Circuits, 2019)

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Min-Su Ahn; Yong-Hun Kim; Yong Jae Lee; Dong-Seok Kang; Sung-Geun Do; Chang-Yong Lee; Gun-hee Cho; Jae-Koo Park; Jae-Sung Kim; et al. (IEEE J. Solid State Circuits, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)

Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond. - Jin Hyun Kim; Shinhaeng Kang; Sukhan Lee 002; Hyeonsu Kim; Woongjae Song; Yuhwan Ro; Seungwon Lee; David Wang 003; Hyunsung Shin; BengSeng Phuah; Jihyun Choi; Jinin So; et al. (HCS, 2021)

Industry's First 7.2 Gbps 512GB DDR5 Module. - Sung Joo Park; Jonghoon J. Kim; Kun Joo; Young-Ho Lee; Kyoungsun Kim; Young-Tae Kim; Woo-Jin Na; IkJoon Choi; Hye-Seung Yu; Wonyoung Kim; Ju-Yeon Jung; Jaejun Lee; et al. (HCS, 2021)

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Donghun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (A-SSCC, 2023)

A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. - Daehyun Kwon; Heon Su Jeong; Jaemin Choi; Wijong Kim; Jae Woong Kim; Junsub Yoon; Jungmin Choi; Sanguk Lee; Hyunsub Norbert Rie; Jin-Il Lee; Jongbum Lee; Taeseong Jang; et al. (ISSCC, 2023)

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. - IkJoon Choi; Seunghwan Hong; Kihyun Kim; Jeongsik Hwang; Seunghan Woo; Young-Sang Kim; Cheongryong Cho; Eun-Young Lee; Hun-Jae Lee; Min-Su Jung; Hee-Yun Jung; Ju-Seong Hwang; et al. (ISSCC, 2024)