MetaCore: An Application Specific DSP Development System. - Jin-Hyuk Yang; Byoung-Woon Kim; Sang-Jun Nam; Jang-Ho Cho; Sung-Won Seo; Chang-Ho Ryu; Young-Su Kwon; Dae-Hyun Lee; Jong-Yeol Lee; Jong-Sun Kim; Hyun-Dhong Yoon; Jae-Yeol Kim; et al. (DAC, 1998)

A New Single-Clock Flip-Clop for Half-Swing Clocking. - Young-Su Kwon; Bong-Il Park; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 1999)

MDSP-II: a 16-bit DSP with mobile communication accelerator. - Byoung-Woon Kim; Jin-Hyuk Yang; Chan-Soo Hwang; Young-Su Kwon; Keun-Moo Lee; In-Hyoung Kim; Yong-Hoon Lee; Chong-Min Kyung (IEEE J. Solid State Circuits, 1999)

DIVA: dual-issue VLIW architecture with media instructions for image processing. - Sang-Joon Nam; Young-Su Kwon; Yeon-Ho Im; Kyung-Ku Kang; Chong-Min Kyung (IEEE Trans. Consumer Electron., 1999)

A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. - Young-Su Kwon; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 2000)

Fast development of source-level debugging system using hardware emulation (short paper). - Sang-Joon Nam; Jun-Hee Lee; Byoung-Woon Kim; Yeon-Ho Im; Young-Su Kwon; Kyong-Gu Kang; Chong-Min Kyung (ASP-DAC, 2000)

FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit. - Sang-Joon Nam; Byoung-Woon Kim; Yeon-Ho Im; Young-Su Kwon; Jun-Hee Lee; Young-Wook Cheon; Sung-Jae Byun; Dae-Hyun Lee; Chong-Min Kyung (CICC, 2000)

Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. - Young-Su Kwon; In-Cheol Park; Chong-Min Kyung (ICIP, 2000)

MetaCore: an application-specific programmable DSP development system. - Jin-Hyuk Yang; Byoung-Woon Kim; Sang-Joon Nam; Young-Su Kwon; Dae-Hyun Lee; Jong-Yeol Lee; Chan-Soo Hwang; Yong Hoon Lee; Seung Ho Hwang; In-Cheol Park; Chong-Min Kyung (IEEE Trans. Very Large Scale Integr. Syst., 2000)

SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. - Young-Su Kwon; Bong-Il Park; Chong-Min Kyung (ICCD, 2003)

Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection. - Young-Su Kwon; Woo-Seung Yang; Chong-Min Kyung (VLSI-SOC, 2003)

Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation. - Young-Su Kwon; Jae-Gon Lee; Chong-Min Kyung (ASP-DAC, 2004)

Communication-efficient hardware acceleration for fast functional simulation. - Young-Il Kim; Woo-Seung Yang; Young-Su Kwon; Chong-Min Kyung (DAC, 2004)

Systematic functional coverage metric synthesis from hierarchical temporal event relation graph. - Young-Su Kwon; Young-Il Kim; Chong-Min Kyung (DAC, 2004)

Functional Coverage Metric Generation from Temporal Event Relation Graph. - Young-Su Kwon; Chong-Min Kyung (DATE, 2004)

Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture. - Young-Su Kwon; Chong-Min Kyung (Microprocess. Microsystems, 2004)

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. - Jae-Gon Lee; Woo-Seung Yang; Young-Su Kwon; Young-Il Kim; Chong-Min Kyung (ASP-DAC, 2005)

A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. - Young-Su Kwon; Payam Lajevardi; Anantha P. Chandrakasan; Frank Honoré; Donald E. Troxel (SLIP, 2005)

Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. - Young-Su Kwon; Chong-Min Kyung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture. - Young-Su Kwon; C.-M. Kyung (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A 159.2mW SoC implementation of T-DMB receiver including stacked memories. - Joohyun Lee; Sungdo Kim; Jinkyu Kim; Duckhwan Kim 002; Young-Su Kwon; Minseok Choi; Kihyuk Park; Bontae Koo; Nak-Woong Eum; Hyuckjae Lee (CICC, 2008)

Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor. - Young-Su Kwon; Bontae Koo; Nak-Woong Eum (FPL, 2008)

Standstill Parameter Identification of Vector-Controlled Induction Motor Using Frequency Characteristics of Rotor Bars. - Young-Su Kwon; Jeong-Hum Lee; Sang-Ho Moon; Byung-Ki Kwon; Chang-Ho Choi; Jul-Ki Seok (IAS, 2008)

Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor. - Young-Su Kwon; Bontae Koo; Nak-Woong Eum (ASP-DAC, 2009)

Implmentation of digital audio effect SoC. - Kyungjin Byun; Young-Su Kwon; Bontae Koo; Nak-Woong Eum; Koang-Hui Jeong; Jae-Eul Koo (ICME, 2009)

Transparent session transfer in converged IP Messaging systems. - Young-Su Kwon; Jaehyun Jang; Hyunwoo Lee; Haewook Lee; Bummo Koo; Wuk Kim; Hyeonsang Eom (WTS, 2010)

Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor. - Young-Su Kwon; Nak-Woong Eum (J. Circuits Syst. Comput., 2010)

Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor. - Young-Su Kwon; Nak-Woong Eum (Microprocess. Microsystems, 2010)

A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262. - Jinho Han; Youngsu Kwon; Kyeongjin Byun; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics. - Jinho Han; Youngsu Kwon; Yong Cheol Peter Cho; Hoi-Jun Yoo (A-SSCC, 2017)

A deep learning convolution architecture for simple embedded applications. - Chan Kim; Yong Cheol Peter Cho; Youngsu Kwon (ICCE-Berlin, 2017)

Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture. - Youngsu Kwon; Jeongmin Yang; Yong Cheol Peter Cho; Kyoung-Seon Shin; Jaehoon Chung; Jinho Han; Chun-Gi Lyuh; Hyun-Mi Kim; Chan Kim; Min-Seok Choi (AICAS, 2019)

Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator. - Chan Kim; In San Jeon; Young-Su Kwon; Hyun-Mi Kim; Chun-Gi Lyuh; Yong Cheol Peter Cho; Jeongmin Yang; Jaehoon Chung; Kyoung-Seon Shin; Jinho Han; Min-Seok Choi (ICCE-Berlin, 2019)

AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving. - Youngsu Kwon; Yong Cheol Peter Cho; Jeongmin Yang; Jaehoon Chung; Kyoung-Seon Shin; Jinho Han; Chan Kim; Chun-Gi Lyuh; Hyun-Mi Kim; In San Jeon; Min-Seok Choi (ISOCC, 2019)

HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP. - Je-Seok Ham; Yong Cheol Peter Cho; Ju-Yeob Kim; Chun-Gi Lyuh; Jin-Kyu Kim; Jinho Han; Youngsu Kwon (HPC Asia, 2021)

Live Demonstration: A Neural Processor for AI Acceleration. - Hyeji Kim; Jaehoon Chung; Kyoung-Seon Shin; Chun-Gi Lyuh; Hyun-Mi Kim; Chan Kim; Yong Cheol Peter Cho; Jeongmin Yang; Je-Seok Ham; Minseok Choi; Jinho Han; Youngsu Kwon (ISCAS, 2021)

ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System. - Jinho Han; Chun-Gi Lyuh; Kyeongsun Shin; Hyun-Mi Kim; Hyunjeong Kwon; Jaehoon Chung; Yong Cheol Peter Cho; Jinkyu Kim; Jeonghui Suk; Chan Kim; Minseok Choi; Youngsu Kwon (AICAS, 2022)

M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations. - Won Jeon; Yong Cheol Peter Cho; Hyun-Mi Kim; Hyeji Kim; Jaehoon Chung; Ju-Yeob Kim; Miyoung Lee; Chun-Gi Lyuh; Jinho Han; Youngsu Kwon (AICAS, 2022)

AIWareK: Compiling PyTorch Model for AI Processor Using MLIR Framework. - Hyunjeong Kwon; Hyun-Mi Kim; Chun-Gi Lyuh; Jin-Kyu Kim; Jinho Han; Youngsu Kwon (AICAS, 2022)

Backward Graph Construction and Lowering in DL Compiler for Model Training on AI Accelerators. - Hyunjeong Kwon; Youngsu Kwon; Jinho Han (ISOCC, 2022)

Chiplet Heterogeneous-Integration AI Processor. - Youngsu Kwon; Jinho Han; Yong Cheol Peter Cho; Juyeob Kim; Jaehoon Chung; Jaewoong Choi; Sujin Park; Igyeong Kim; Hyunjeong Kwon; Jinkyu Kim; Hyunmi Kim; Won Jeon; et al. (ICEIC, 2023)

2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform. - Sujin Park; Yi-Gyeong Kim; Young-Deuk Jeon; Min-Hyung Cho; Jinho Han; Youngsu Kwon (ICEIC, 2023)

ABSX: The Chiplet Hyperscale AI Processing Unit for Energy-Efficient High-Performance AI Processing. - Youngsu Kwon (ISOCC, 2023)

DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration. - Sujin Park; Young-Deuk Jeon; Yi-Gyeong Kim; Min-Hyung Cho; Jinho Han; Jaehoon Chung; Jaewoong Choi; Youngsu Kwon (ISOCC, 2023)

Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect. - Jiwon Yoon; Hyunwoo Kim; Boogyo Sim; Hyunwook Park; Yi-Gyeong Kim; Sujin Park; Youngsu Kwon; Joungho Kim (ISOCC, 2023)