An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications. - Youngbog Yoon; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. - Youngbog Yoon; Hyunsu Park; Chulwoo Kim (IEEE Trans. Circuits Syst., 2020)

Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies. - Youngbog Yoon; Daeyong Han; Shinho Chu; Sangho Lee; Jaeduk Han; Junhyun Chun (DATE, 2021)