A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. - Dong-Uk Lee; Ho Sung Cho; Jihwan Kim; Young Jun Ku; Sangmuk Oh; Chul Dae Kim; Hyun Woo Kim; Wooyoung Lee; Tae-Kyun Kim 001; Tae Sik Yun; Min Jeong Kim; SeungGyeon Lim; et al. (ISSCC, 2020)

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Ho Sung Cho; Tae-Sik Yun; Sangjin Byeon; Young Jun Koo; Sang-Sic Yoon; Dong-Uk Lee; Seokwoo Choi; Ji Hwan Park; Jinhyung Lee; Kyungjun Cho; Junil Moon; et al. (ISSCC, 2022)