Optimal workpiece positioning in flexible fixtures for thin-walled components. - Minh Duc Do; Younghoon Son; Hae-Jin Choi (Comput. Aided Des., 2018)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package. - Youngmin Jo; Anil Kavala; Tongsung Kim; Byung-Kwan Chun; Jungjune Park; Taesung Lee; Jungmin Seo; Manjae Yang; Taehyeon Park; Hyunjin Kwon; Cheolhui Lee; Younghoon Son; et al. (VLSI Technology and Circuits, 2023)