A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth. - Jong-Bum Park; Sang-Min Yoo; Se-Won Kim; Young-Jae Cho 001; Seung-Hoon Lee 006 (IEEE J. Solid State Circuits, 2004)

An 8b 240 MS/s 1.36 mm2 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs. - Se-Won Kim; Young-Jae Cho 001; Kyung-Hoon Lee; Seung-Hoon Lee 006; Jae-Yup Lee; Hyun-Chul Noh; Hee-Sub Lee (ISCAS (4), 2005)

An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References. - Young-Jae Cho 001; Hyuen-Hee Bae; Seung-Hoon Lee 006 (IEICE Trans. Electron., 2005)

An 11b 70-MHz 1.2-mm2 49-mW 0.18-μm CMOS ADC with on-chip current/voltage references. - Young-Jae Cho 001; Seung-Hoon Lee 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems. - Young-Jae Cho 001; Kyung-Hoon Lee; Hee-Cheol Choi; Young-Ju Kim; Kyoung-Jun Moon; Seung-Hoon Lee 006; Seok-Bong Hyun; Seong-Su Park (APCCAS, 2006)

A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter. - Kyung-Hoon Lee; Young-Jae Cho 001; Hee-Cheol Choi; Yong-Hyun Park; Doo-Hwan Sa; Young-Lok Kim; Seung-Hoon Lee 006 (APCCAS, 2006)

A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors. - Young-Jae Cho 001; Kyung-Hoon Lee; Hee-Cheol Choi; Seung-Hoon Lee 006; Kyoung-Ho Moon; Jae-Whui Kim (CICC, 2006)

A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications. - Young-Jae Cho 001; Doo-Hwan Sa; Yong-Woo Kim; Kyung-Hoon Lee; Hee-Cheol Choi; Seung-Hoon Lee 006; Young-Deuk Jeon; Seung-Chul Lee; Jong-Kee Kwon (CICC, 2006)

An Embedded 8b 240 MS/s 1.36 mm2 104 mW 0.18 µCMOS ADC for DVDs with Dual-Mode Inputs. - Young-Jae Cho 001; Se-Won Kim; Kyung-Hoon Lee; Hee-Cheol Choi; Young-Lok Kim; Seung-Hoon Lee 006 (IEICE Trans. Electron., 2006)

A 10b 100 MS/s 1.4 mm256 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors. - Byoung-Han Min; Young-Jae Cho 001; Hee-Sung Chae; Hee-Won Park; Seung-Hoon Lee 006 (IEICE Trans. Electron., 2006)

A 10 b 200 MS/s 1.8 mm2 83 mW 0.13µm CMOS ADC Based on Highly Linear Integrated Capacitors. - Young-Ju Kim; Young-Jae Cho 001; Doo-Hwan Sa; Seung-Hoon Lee 006 (IEICE Trans. Electron., 2007)

An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. - Seung-Yong Lim; Raymond Mabilangan; Dong-Jin Chang; Young-Jae Cho 001; Michael Choi 001; Seung-Tak Ryu (A-SSCC, 2021)

A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. - Seung-Yeob Baek 002; Il-Hoon Jang; Michael Choi 001; Hyungdong Roh; Woongtaek Lim; Youngjae Cho 001; Jongshin Shin (ISSCC, 2021)

A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET. - Byeongwoo Koo; Sunghan Do; Sang-Pil Nam; Heewook Shin; Sungno Lee; Eunhye Oh; Jaemin Hong; Jung-Ho Lee; Youngjae Cho 001; Michael Choi 001; Jongshin Shin (VLSI Technology and Circuits, 2022)

An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application. - Kyung-Hoon Lee; Jinwoo Park; Younghyo Park; Byeongwoo Koo; Sunghan Do; Woongtaek Lim; Sungno Lee; Hyochul Shin; Eunhye Oh; Youngjae Cho 001; Michael Choi 001; Jongshin Shin (VLSI Technology and Circuits, 2022)

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. - Kyoung-Jun Moon; Dong-Ryeol Oh; Young-Hyo Park; Kyung-Hoon Lee; Sun-Jae Park; Sung-No Lee; Hee-Chang Hwang; Hyo-Chul Shin; Young-Jae Cho 001; Michael Choi 001; Jongshin Shin (VLSI Technology and Circuits, 2022)

A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. - Kent Edrian Lozada; Dong-Hun Lee; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho 001; Michael Choi 001; Seung-Tak Ryu (A-SSCC, 2023)

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA. - Bo Gao; Lizhen Zhang; Raymond Mabilangan; Chang-Un Park; Kent Edrian Lozada; Ho-Jin Kim; Youngjae Cho 001; Michael Choi 001; Seung-Tak Ryu (A-SSCC, 2024)

3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor. - Sangheon Lee; Jinwoo Park; Junsang Park; Sangkyu Lee; Jungho Lee; Youngjae Cho 001; Michael Choi 001; Jongshin Shin (ISSCC, 2024)

A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving -85dBc IMD3 in 5nm FinFET. - Byeongwoo Koo; Sunghan Do; Sangkyu Lee; Sang-Pil Nam; Heewook Shin; Saemin Im; Hyochul Shin; Sungno Lee; Junsang Park; Jungho Lee; Youngjae Cho 001; Michael Choi 001; et al. (VLSI Technology and Circuits, 2024)

A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho 001; Michael Choi 001; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET. - Junsang Park; Jinwoo Park; Jaemin Hong; Sun-Jae Park; Dongsuk Lee; Sungno Lee; Hyochul Shin; Kyung-Hoon Lee; Byeongwoo Koo; Youngjae Cho 001; Michael Choi 001; Jongshin Shin (VLSI Technology and Circuits, 2024)

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. - Dong-Hun Lee; Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho 001; Michael Choi 001; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)

High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications. - Jihun Choi 001; Sangwook Na; Hojin Kim; Hyungdong Roh; Youngjae Cho 001; Michael Choi 001; Min-Seong Choo; Jeongjin Roh (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho 001; Michael Choi 001; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2025)

A 12-Bit 600-MS/s Pipelined ADC With Two-Stage High-Gain Dynamic Amplifier in 28-nm CMOS. - Bo Gao; Raymond Mabilangan; Chang-Un Park; Kent Edrian Lozada; Ho-Jin Kim; Youngjae Cho 001; Michael Choi 001; Seung-Tak Ryu (IEEE Trans. Circuits Syst. I Regul. Pap., 2026)