A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. - Seung-Yeob Baek 002; Il-Hoon Jang; Michael Choi; Hyungdong Roh; Woongtaek Lim; Youngjae Cho; Jongshin Shin (ISSCC, 2021)

Predict Sequential Credit Card Delinquency with VaDE-Seq2Seq. - Yeongmin Kim; Youngjae Cho; Hanbit Lee; Il-Chul Moon (SMC, 2021)

A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET. - Byeongwoo Koo; Sunghan Do; Sang-Pil Nam; Heewook Shin; Sungno Lee; Eunhye Oh; Jaemin Hong; Jung-Ho Lee; Youngjae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2022)

An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application. - Kyung-Hoon Lee; Jinwoo Park; Younghyo Park; Byeongwoo Koo; Sunghan Do; Woongtaek Lim; Sungno Lee; Hyochul Shin; Eunhye Oh; Youngjae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2022)

A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. - Kent Edrian Lozada; Dong-Hun Lee; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2023)

SAAL: Sharpness-Aware Active Learning. - Yoon-Yeong Kim; Youngjae Cho; JoonHo Jang; Byeonghu Na; Yeongmin Kim; Kyungwoo Song; Wanmo Kang; Il-Chul Moon (ICML, 2023)

Make Prompts Adaptable: Bayesian Modeling for Vision-Language Prompt Learning with Data-Dependent Prior. - Youngjae Cho; HeeSun Bae; Seungjae Shin; Yeo Dong Youn; Weonyoung Joo; Il-Chul Moon (AAAI, 2024)

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA. - Bo Gao; Lizhen Zhang; Raymond Mabilangan; Chang-Un Park; Kent Edrian Lozada; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2024)

3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor. - Sangheon Lee; Jinwoo Park; Junsang Park; Sangkyu Lee; Jungho Lee; Youngjae Cho; Michael Choi; Jongshin Shin (ISSCC, 2024)

A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving -85dBc IMD3 in 5nm FinFET. - Byeongwoo Koo; Sunghan Do; Sangkyu Lee; Sang-Pil Nam; Heewook Shin; Saemin Im; Hyochul Shin; Sungno Lee; Junsang Park; Jungho Lee; Youngjae Cho; Michael Choi; et al. (VLSI Technology and Circuits, 2024)

A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET. - Junsang Park; Jinwoo Park; Jaemin Hong; Sun-Jae Park; Dongsuk Lee; Sungno Lee; Hyochul Shin; Kyung-Hoon Lee; Byeongwoo Koo; Youngjae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2024)

Revisiting DDIM Inversion for Controlling Defect Generation by Disentangling the Background. - Youngjae Cho; Gwangyeol Kim; Sirojbek Safarov; Seongdeok Bang; Jaewoo Park (CoRR, 2024)

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. - Dong-Hun Lee; Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)

High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications. - Jihun Choi; Sangwook Na; Hojin Kim; Hyungdong Roh; Youngjae Cho; Michael Choi; Min-Seong Choo; Jeongjin Roh (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2025)