A mixed-structure delay locked-loop with wide range and fast locking. - Youngkwon Jo; Yong Shim; Soo Hwan Kim; Suki Kim; Kwanjun Cho (ISCAS, 2006)

A register controlled delay locked loop using a TDC and a new fine delay line scheme. - Yong Shim; Youngkwon Jo; Soo Hwan Kim; Suki Kim; Kwanjun Cho (ISCAS, 2006)

Digitally Controlled Duty Cycle Corrector with 1 ps Resolution. - Youngkwon Jo; Hoyoung Park; Sanghyuk Yang; Suki Kim; Kwang-Hyun Baek (IEICE Trans. Electron., 2007)

An intra-panel interface using three transmission lines for flat panel displays. - Youngkwon Jo; Hoyoung Park; Suki Kim; Kwang-Hyun Baek (IEICE Electron. Express, 2008)

A low-jitter BMCDR for half-rate PON systems. - Dong-Hyun Yoon; Yohan Hong; Jae-Hun Jung; Youngkwon Jo; Kwang-Hyun Baek (IEICE Electron. Express, 2017)