Special purpose array processor for digital logic simulation. - Youngmin Hur; Stephen A. Szygenda (Annual Simulation Symposium, 1995)

Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. - Youngmin Hur; Stephen A. Szygenda; E. Scott Fehr; Granville E. Ott; Sungho Kang 001 (HPCA, 1995)

A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling. - Youngmin Hur; Stephen A. Szygenda (Annual Simulation Symposium, 1996)

A Graphical Simulation and Automatic Model Generation System. - Youngmin Hur; Stephen A. Szygenda (ESM, 1996)

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. - Sungho Kang 001; Youngmin Hur; Stephen A. Szygenda (VLSI Design, 1996)

Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. - Youngmin Hur; Saghir A. Shaikh; Silvian Goldenberg; Dominik Kacprzak; Stephen A. Szygenda (Annual Simulation Symposium, 1997)