An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. - Yongjoo Kim; Kyuseok Kim; Youngsoo Shin; Taekyoon Ahn; Wonyong Sung; Kiyoung Choi; Soonhoi Ha (ASP-DAC, 1995)

Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. - Yongjoo Kim; Youngsoo Shin; Kyuseok Kim; Jae-Hee Won; Kiyoung Choi (ISCAS, 1995)

Thread-based software synthesis for embedded system design. - Youngsoo Shin; Kiyoung Choi (ED&TC, 1996)

Software synthesis through task decomposition by dependency analysis. - Youngsoo Shin; Kiyoung Choi (ICCAD, 1996)

An integrated hardware-software cosimulation environment with automated interface generation. - Kyuseok Kim; Yongjoo Kim; Youngsoo Shin; Kiyoung Choi (RSP, 1996)

Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. - Youngsoo Shin; Kiyoung Choi (CODES, 1997)

Rate Assignment for Embedded Reactive Real-Time Systems. - Youngsoo Shin; Kiyoung Choi (EUROMICRO, 1998)

Partial bus-invert coding for power optimization of system level bus. - Youngsoo Shin; Soo-Ik Chae; Kiyoung Choi (ISLPED, 1998)

An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping. - Yongjoo Kim; Kyuseok Kim; Youngsoo Shin; Taekyoon Ahn; Kiyoung Choi (Des. Autom. Embed. Syst., 1998)

Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. - Youngsoo Shin; Kiyoung Choi (DAC, 1999)

Narrow bus encoding for low power systems. - Youngsoo Shin; Kiyoung Choi (ASP-DAC, 2000)

Schedulability-driven performance analysis of multiple mode embedded real-time systems. - Youngsoo Shin; Daehong Kim; Kiyoung Choi (DAC, 2000)

Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. - Youngsoo Shin; Kiyoung Choi; Takayasu Sakurai (ICCAD, 2000)

Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems. - Youngsoo Shin; Hiroshi Kawaguchi 001; Takayasu Sakurai (CICC, 2001)

Coupling-Driven Bus Design for Low-Power Application-Specific Systems. - Youngsoo Shin; Takayasu Sakurai (DAC, 2001)

Estimation of power distribution in VLSI interconnects. - Youngsoo Shin; Takayasu Sakurai (ISLPED, 2001)

Partial bus-invert coding for power optimization of application-specific systems. - Youngsoo Shin; Soo-Ik Chae; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Narrow bus encoding for low-power DSP systems. - Youngsoo Shin; Kiyoung Choi; Young-Hoon Chang (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Power-conscious Scheduling for Real-time Embedded Systems Design. - Youngsoo Shin; Kiyoung Choi; Takayasu Sakurai (VLSI Design, 2001)

Early analysis tools for system-on-a-chip design. - John A. Darringer; Reinaldo A. Bergamaschi; Subhrajit Bhattacharya; Daniel Brand; Andreas Herkersdorf; Joseph K. Morrell; Indira Nair; Patricia Sagmeister; Youngsoo Shin (IBM J. Res. Dev., 2002)

Power distribution analysis of VLSI interconnects using model orderreduction. - Youngsoo Shin; Takayasu Sakurai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

SEAS: a system for early analysis of SoCs. - Reinaldo A. Bergamaschi; Youngsoo Shin; Nagu R. Dhanwada; Subhrajit Bhattacharya; William E. Dougherty; Indira Nair; John A. Darringer; Sarala Paliwal (CODES+ISSS, 2003)

Architecting voltage islands in core-based system-on-a-chip designs. - Jingcao Hu; Youngsoo Shin; Nagu R. Dhanwada; Radu Marculescu (ISLPED, 2004)

Power-aware slack distribution for hierarchical VLSI design. - Hyung-Ock Kim; Youngsoo Shin (ISCAS (4), 2005)

Analysis of power consumption in VLSI global interconnects. - Youngsoo Shin; Hyung-Ock Kim (ISCAS (5), 2005)

A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. - Subhrajit Bhattacharya; John A. Darringer; Daniel L. Ostapko; Youngsoo Shin (ISQED, 2005)

μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. - Hiroshi Kawaguchi 001; Youngsoo Shin; Takayasu Sakurai (IEEE Trans. Multim., 2005)

Analysis and optimization of gate leakage current of power gating circuits. - Hyung-Ock Kim; Youngsoo Shin (ASP-DAC, 2006)

Physical design methodology of power gating circuits for standard-cell-based design. - Hyung-Ock Kim; Youngsoo Shin; Hyuk Kim; Iksoo Eo (DAC, 2006)

Power Analysis of VLSI Interconnect with RLC Tree Models and Model Reduction. - Youngsoo Shin; Junghyup Lee (J. Circuits Syst. Comput., 2006)

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. - Youngsoo Shin; Sewan Heo; Hyung-Ock Kim; Jung Yun Choi (ASP-DAC, 2007)

Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits. - Jun Seomun; Jaehyun Kim; Youngsoo Shin (DAC, 2007)

Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. - Jaehyun Kim; Youngsoo Shin (ICCAD, 2007)

Lookup Table-Based Adaptive Body Biasing of Multiple Macros. - Byunghee Choi; Youngsoo Shin (ISQED, 2007)

Cell-Based Semicustom Design of Zigzag Power Gating Circuits. - Youngsoo Shin; Hyung-Ock Kim (ISQED, 2007)

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications. - Hyung-Ock Kim; Youngsoo Shin (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. - Youngsoo Shin; Sewan Heo; Hyung-Ock Kim; Jung Yun Choi (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. - Jinseob Jeong; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2008)

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. - Seungwhun Paik; Youngsoo Shin (DAC, 2008)

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. - Hyein Lee 003; Seungwhun Paik; Youngsoo Shin (ICCAD, 2008)

3-D thermal simulation with dynamic power profiles. - Eunjoo Choi; Youngsoo Shin (ISCAS, 2008)

Power-gating-aware high-level synthesis. - Eunjoo Choi; Changsik Shin; Taewhan Kim; Youngsoo Shin (ISLPED, 2008)

Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits. - Jun Seomun; Jae-Hyun Kim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Register allocation for high-level synthesis using dual supply voltages. - Insup Shin; Seungwhun Paik; Youngsoo Shin (DAC, 2009)

HLS-l: High-level synthesis of high performance latch-based circuits. - Seungwhun Paik; Insup Shin; Youngsoo Shin (DATE, 2009)

Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. - Seonggwan Lee; Seungwhun Paik; Youngsoo Shin (ICCAD, 2009)

Frequency and yield optimization using power gates in power-constrained designs. - Nam Sung Kim; Jun Seomun; Abhishek A. Sinkar; Jungseob Lee; Tae Hee Han; Ken Choi; Youngsoo Shin (ISLPED, 2009)

ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. - Eunjoo Choi; Changsik Shin; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. - Youngsoo Shin; Seungwhun Paik; Hyung-Ock Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates. - Jaehyun Kim; Chungki Oh; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2009)

Statistical time borrowing for pulsed-latch circuit designs. - Seungwhun Paik; Lee-eun Yu; Youngsoo Shin (ASP-DAC, 2010)

Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. - Jun Seomun; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2010)

Synthesis and implementation of active mode power gating circuits. - Jun Seomun; Insup Shin; Youngsoo Shin (DAC, 2010)

Wakeup synthesis and its buffered tree construction for power gating circuit designs. - Seungwhun Paik; Sangmin Kim; Youngsoo Shin (ISLPED, 2010)

Lookup Table-Based Adaptive Body biasing of Multiple Macros for Process Variation Compensation and Low Leakage. - Byunghee Choi; Youngsoo Shin (J. Circuits Syst. Comput., 2010)

Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. - Hyein Lee 003; Seungwhun Paik; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. - Seungwhun Paik; Insup Shin; Taewhan Kim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. - Youngsoo Shin; Jun Seomun; Kyu-Myung Choi; Takayasu Sakurai (ACM Trans. Design Autom. Electr. Syst., 2010)

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. - Hyung-Ock Kim; Bong Hyun Lee; Jong-Tae Kim; Jung Yun Choi; Kyu-Myung Choi; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. - Donkyu Baek; Insup Shin; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2011)

Pulser gating: A clock gating of pulsed-latch circuits. - Sangmin Kim; Inhak Han; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2011)

Thermal signature: a simple yet accurate thermal index for floorplan optimization. - Jaeha Kung; Inhak Han; Sachin S. Sapatnekar; Youngsoo Shin (DAC, 2011)

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. - Seungwhun Paik; Gi-Joon Nam; Youngsoo Shin (ICCAD, 2011)

Compact thermal models: Assessment and pitfalls. - Jaeha Kung; Youngsoo Shin (ISOCC, 2011)

Pulsed-Latch Circuits: A New Dimension in ASIC Design. - Youngsoo Shin; Seungwhun Paik (IEEE Des. Test Comput., 2011)

Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. - Lee-eun Yu; Changsik Shin; Seungwhun Paik; Jing-Jia Liou; Youngsoo Shin (J. Circuits Syst. Comput., 2011)

Pulsed-Latch Aware Placement for Timing-Integrity Optimization. - Yi-Lin Chuang; Sangmin Kim; Youngsoo Shin; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Retiming Pulsed-Latch Circuits With Regulating Pulse Width. - Seungwhun Paik; Seonggwan Lee; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Design and Optimization of Power-Gated Circuits With Autonomous Data Retention. - Jun Seomun; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Introducing irregularity to routing architecture of structured ASIC for better routability. - Insup Shin; Donkyu Baek; Youngsoo Shin (FPT, 2012)

Gate delay modeling for static timing analysis of body-biased circuits. - Donkyu Baek; Insup Shin; Youngsoo Shin (ICICDT, 2012)

Synthesis of clock gating logic through factored form matching. - Inhak Han; Youngsoo Shin (ICICDT, 2012)

Clock Gating Synthesis of Pulsed-Latch Circuits. - Seungwhun Paik; Inhak Han; Sangmin Kim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Synthesis of Active-Mode Power-Gating Circuits. - Jun Seomun; Insup Shin; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating. - Nam Sung Kim; Abhishek A. Sinkar; Jun Seomun; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2012)

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. - Insup Shin; Seungwhun Paik; Dongwan Shin; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Pulsed-latch ASIC synthesis in industrial design flow. - Sangmin Kim; Duckhwan Kim 001; Youngsoo Shin (ASP-DAC, 2013)

Analysis and minimization of short-circuit current in mesh clock network. - Seongbo Shim; Minyoung Mo; Sangmin Kim; Youngsoo Shin (ICCD, 2013)

Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. - Inhak Han; Youngsoo Shin (ICICDT, 2013)

A pipeline architecture with 1-cycle timing error correction for low voltage operations. - Insup Shin; Jae-Joon Kim; Yu-Shiang Lin; Youngsoo Shin (ISLPED, 2013)

Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. - Donkyu Baek; Insup Shin; Youngsoo Shin (J. Circuits Syst. Comput., 2013)

Lithographic defect aware placement using compact standard Cells without inter-cell margin. - Seongbo Shim; Yoojong Lee; Youngsoo Shin (ASP-DAC, 2014)

Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. - Insup Shin; Jae-Joon Kim; Youngsoo Shin (ASP-DAC, 2014)

Design and Optimization of Multiple-Mesh Clock Network. - Jinwook Jung; Dongsoo Lee; Youngsoo Shin (VLSI-SoC (Selected Papers), 2014)

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. - Youngsoo Shin; Insup Shin; Donkyu Baek; Duckhwan Kim 001; Seungwhun Paik (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Simplifying Clock Gating Logic by Matching Factored Forms. - Inhak Han; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Identifying redundant inter-cell margins and its application to reducing routing congestion. - Woohyun Chung; Seongbo Shim; Youngsoo Shin (DATE, 2015)

Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization. - Seongbo Shim; Woohyun Chung; Youngsoo Shin (ICCAD, 2015)

Physical synthesis of DNA circuits with spatially localized gates. - Jinwook Jung; Daijoon Hyun; Youngsoo Shin (ICCD, 2015)

Physical design and mask optimization for directed self-assembly lithography (DSAL). - Seongbo Shim; Youngsoo Shin (VLSI-SoC, 2015)

Message from the technical program chairs. - Youngsoo Shin; Chi-Ying Tsui (VLSI-SoC, 2015)

Prosocial Activists in SNS: The Impact of Isomorphism and Social Presence on Prosocial Behaviors. - Youngsoo Shin; Bumho Lee; Jinwoo Kim (Int. J. Hum. Comput. Interact., 2015)

An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model. - Seongbo Shim; Jae Wook Lee; Youngsoo Shin (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. - Insup Shin; Jae-Joon Kim; Youngsoo Shin (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Machine learning (ML)-based lithography optimizations. - Seongbo Shim; Suhyeong Choi; Youngsoo Shin (APCCAS, 2016)

Buffer insertion to remove hold violations at multiple process corners. - Inhak Han; Daijoon Hyun; Youngsoo Shin (ASP-DAC, 2016)

Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography. - Seongbo Shim; Youngsoo Shin (ASP-DAC, 2016)

Localized DNA circuit design with majority gates. - Jinwook Jung; Youngsoo Shin (BioCAS, 2016)

Redundant via insertion for multiple-patterning directed-self-assembly lithography. - Seongbo Shim; Woohyun Chung; Youngsoo Shin (DAC, 2016)

Redundant via insertion in directed self-assembly lithography. - Woohyun Chung; Seongbo Shim; Youngsoo Shin (DATE, 2016)

OWARU: free space-aware timing-driven incremental placement. - Jinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin (ICCAD, 2016)

Register grouping for synthesis of clock gating logic. - Inhak Han; Jonggyu Kim; Joonhwan Yi; Youngsoo Shin (ICICDT, 2016)

Placement optimization for MP-DSAL compliant layout. - Seongbo Shim; Woohyun Chung; Youngsoo Shin (ICICDT, 2016)

Crosslink insertion for minimizing OCV clock skew. - Kiwon Yoon; Seongbo Shim; Youngsoo Shin (ISCAS, 2016)

Area efficient neuromorphic circuit based on stochastic computation. - Kiwon Yoon; Suhyeong Choi; Youngsoo Shin (ISOCC, 2016)

Wakeup scheduling and its buffered tree synthesis for power gating circuits. - Sangmin Kim; Seungwhun Paik; Seokhyeong Kang; Youngsoo Shin (Integr., 2016)

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. - Sangmin Kim; Seokhyeong Kang; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2016)

One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. - Insup Shin; Jae-Joon Kim; Yu-Shiang Lin; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization. - Jaewoo Seo; Jinwook Jung; Sangmin Kim; Youngsoo Shin (DAC, 2017)

Cut mask optimization for multi-patterning directed self-assembly lithography. - Wachirawit Ponghiran; Seongbo Shim; Youngsoo Shin (DATE, 2017)

Timing-aware wire width optimization for SADP process. - Youngsoo Song; Sangmin Kim; Youngsoo Shin (DATE, 2017)

Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning. - Youngsoo Song; Jinwook Jung; Youngsoo Shin (ACM Great Lakes Symposium on VLSI, 2017)

Clock tree optimization through selective airgap insertion. - Daijoon Hyun; Wachirawit Ponghiran; Youngsoo Shin (ISQED, 2017)

Redundant Via insertion in SADP process with cut merging and optimization. - Youngsoo Song; Jinwook Jung; Youngsoo Shin (VLSI-SoC, 2017)

Design for experience innovation: understanding user experience in new product development. - Youngsoo Shin; Chaerin Im; Hyosun Oh; Jinwoo Kim (Behav. Inf. Technol., 2017)

Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography. - Seongbo Shim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Lithography Defect Probability and Its Application to Physical Design Optimization. - Seongbo Shim; Woohyun Chung; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Automatic insertion of airgap with design rule constraints. - Daijoon Hyun; Youngsoo Shin (ASP-DAC, 2018)

Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires. - Kiwon Yoon; Daijoon Hyun; Youngsoo Shin (ACM Great Lakes Symposium on VLSI, 2018)

Library Optimization for Near-Threshold Voltage Design. - Daijoon Hyun; Jaewoo Seo; Youngsoo Shin (ISCAS, 2018)

Transient Clock Power Estimation of Pre-CTS Netlist. - Yonghwi Kwon 002; Jinwook Jung; Inhak Han; Youngsoo Shin (ISCAS, 2018)

Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits. - Jingon Lee; Jinwook Jung; Youngsoo Shin (ISCAS, 2018)

Optimization of Machine Learning Guided Optical Proximity Correction. - Joonhyuk Cho; Gangmin Cho; Youngsoo Shin (MWSCAS, 2018)

Data-centered persuasion: Nudging user's prosocial behavior and designing social innovation. - Youngsoo Shin; Jinwoo Kim (Comput. Hum. Behav., 2018)

Recap of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). - Youngsoo Shin (IEEE Des. Test, 2018)

Module grouping to reduce the area of test wrappers in SoCs. - Sangmin Kim; Youngsoo Shin (Integr., 2018)

Memory-Efficient Parametric Semiglobal Matching. - Yeongmin Lee; Min-Gyu Park; Youngbae Hwang; Youngsoo Shin; Chong-Min Kyung (IEEE Signal Process. Lett., 2018)

OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. - Jinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Electrothermal Analysis With Nonconvective Boundary Conditions. - Suhyeong Choi; Seongbo Shim; Youngsoo Shin (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. - Inhak Han; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2018)

Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning. - Daijoon Hyun; Yuepeng Fan; Youngsoo Shin (DATE, 2019)

Clock Gating Synthesis of Netlist with Cyclic Logic Paths. - Yonghwi Kwon 002; Inhak Han; Youngsoo Shin (ICCAD, 2019)

Endurance Enhancement of Multi-Level Cell Phase Change Memory. - Cheongwon Lee; Youngsoo Song; Youngsoo Shin (ICCAD, 2019)

Standard Cell Layout Design and Placement Optimization for TFET-Based Circuits. - Youngsoo Song; Jinwook Jung; Youngsoo Shin (ISCAS, 2019)

Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization. - Daijoon Hyun; Younggwang Jung; Youngsoo Shin (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Neural Network Classifier-Based OPC With Imbalanced Training Data. - Suhyeong Choi; Seongbo Shim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Integrated Approach of Airgap Insertion for Circuit Timing Optimization. - Daijoon Hyun; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2019)

Integrated Latch Placement and Cloning for Timing Optimization. - Jinwook Jung; Gi-Joon Nam; Woohyun Chung; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2019)

Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning. - Youngsoo Song; Daijoon Hyun; Jingon Lee; Jinwook Jung; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2019)

Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimization. - Younggwang Jung; Daijoon Hyun; Youngsoo Shin (ASP-DAC, 2020)

Fast ECO Leakage Optimization Using Graph Convolutional Network. - Wonjae Lee; Yonghwi Kwon 002; Youngsoo Shin (ACM Great Lakes Symposium on VLSI, 2020)

Pre-layout clock tree estimation and optimization using artificial neural network. - Sunwha Koh; Yonghwi Kwon 002; Youngsoo Shin (ISLPED, 2020)

PENCODER: Design for Prospective Memory and Older Adults. - Youngsoo Shin; Ruth Barankevich; Jina Lee; Saleh Kalantari (CHI Extended Abstracts, 2021)

Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network. - Sunwha Koh; Younggwang Jung; Daijoon Hyun; Youngsoo Shin (ISCAS, 2021)

Dynamic IR Drop Prediction Using Image-to-Image Translation Neural Network. - Yonghwi Kwon 002; Giyoon Jung; Daijoon Hyun; Youngsoo Shin (ISCAS, 2021)

Towards Designing Human-Centered Time Management Interfaces: The Development of 14 UX Design Guidelines for Time-related Experiences in Mobile HCI. - Youngsoo Shin; Jungkyoon Yoon (MobileHCI (Extended Abstracts), 2021)

Computational Lithography Using Machine Learning Models. - Youngsoo Shin (IPSJ Trans. Syst. LSI Des. Methodol., 2021)

Supporting Users' Decision-Making Experiences through Hyper-Personalized Human-Technology Interactions. - Youngsoo Shin (onference on Designing Interactive Systems (Companion Volume), 2022)

Fast Prediction of Dynamic IR-Drop Using Recurrent U-Net Architecture. - Yonghwi Kwon 002; Youngsoo Shin (MLCAD, 2022)

Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs. - Daijoon Hyun; Younggwang Jung; Insu Cho; Youngsoo Shin (ASP-DAC, 2023)

Lightning Talk 21: EDA with ML, Rule-Based, or Both? - Youngsoo Shin (DAC, 2023)

Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement. - Younggwang Jung; Daijoon Hyun; Soyoon Choi; Youngsoo Shin (ICCAD, 2023)

Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction. - Byungho Choi; Yonghwi Kwon 002; Umar Afzaal; Youngsoo Shin (ISCAS, 2023)

Block-Level Power Net Routing of Analog Circuit Using Reinforcement Learning. - Taeyoung Kim; Gangmin Cho; Youngsoo Shin (ISCAS, 2023)

Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting. - Wonjae Lee; Insu Cho; Gangmin Cho; Youngsoo Shin (MLCAD, 2023)

AI-EDA: Toward a Holistic Approach to AI-Powered EDA. - Youngsoo Shin (MLCAD, 2023)

Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage. - Yoonsang Song; Gangmin Cho; Wonjae Lee; Youngsoo Shin (MLCAD, 2023)

Too Many or Too Little: Investigating Different Decision-making Experiences of Maximizers and Satisficers in HCIs. - Youngsoo Shin; Jungkyoon Yoon (OZCHI, 2023)

Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints. - Daijoon Hyun; Younggwang Jung; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells. - Daijoon Hyun; Wonjae Lee; JinHyeong Park; Youngsoo Shin (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking. - Daijoon Hyun; Sunwha Koh; Younggwang Jung; Taeyoung Kim; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2023)

Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model. - Seunggyu Lee; Daijoon Hyun; Younggwang Jung; Gangmin Cho; Youngsoo Shin (DATE, 2024)

Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic. - Seunggyu Lee; Wonjae Lee; Youngsoo Shin (ACM Great Lakes Symposium on VLSI, 2024)

Fast and Accurate Curvilinear OPC with ML-Guided Curve Correction. - Seohyun Kim; Gangmin Cho; Shilong Zhang; Youngsoo Shin (ISOCC, 2024)

Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network. - Daijoon Hyun; Younggwang Jung; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs. - Daijoon Hyun; Younggwang Jung; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2024)

An Island Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided Logic. - Umar Afzaal; Seunggyu Lee; Youngsoo Shin (ASP-DAC, 2025)

ML for Computational Lithography: Practical Recipes. - Youngsoo Shin (ASP-DAC, 2025)

Fast and Accurate Analysis of Power Distribution Network Impedance for DRAM Design. - Minseung Shin; Shilong Zhang; Youngsoo Shin (ISCAS, 2025)

Toward personalized AI-powered recommender systems to support users' daily music choice experiences. - Youngsoo Shin; Krithik Ranjan; Michael C. Kowalski; Jungkyoon Yoon (Int. J. Hum. Comput. Stud., 2025)