Timing-aware wire width optimization for SADP process. - Youngsoo Song; Sangmin Kim; Youngsoo Shin (DATE, 2017)

Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning. - Youngsoo Song; Jinwook Jung; Youngsoo Shin (ACM Great Lakes Symposium on VLSI, 2017)

Redundant Via insertion in SADP process with cut merging and optimization. - Youngsoo Song; Jinwook Jung; Youngsoo Shin (VLSI-SoC, 2017)

Endurance Enhancement of Multi-Level Cell Phase Change Memory. - Cheongwon Lee; Youngsoo Song; Youngsoo Shin (ICCAD, 2019)

Standard Cell Layout Design and Placement Optimization for TFET-Based Circuits. - Youngsoo Song; Jinwook Jung; Youngsoo Shin (ISCAS, 2019)

Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning. - Youngsoo Song; Daijoon Hyun; Jingon Lee; Jinwook Jung; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2019)