14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. - Hyojun Kim; Jinwoo Sang; Hyunik Kim; Youngwoo Jo; Taeik Kim; Hojin Park; SeongHwan Cho (ISSCC, 2015)

A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation. - Youngwoo Jo; Hyojun Kim; SeongHwan Cho (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. - Jusung Lee; Youngwoo Jo; Wonsik Yu; WooSeok Kim; Michael Choi; Sanghune Park; Jongshin Shin (CICC, 2023)