Stochastic glitch elimination considering path correlation. - Youse Kim; Naeun Zang; Juho Kim (SoCC, 2007)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. - Jae-Woo Im; Woopyo Jeong; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (ISSCC, 2015)

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. - Woopyo Jeong; Jae-Woo Im; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (IEEE J. Solid State Circuits, 2016)