An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application. - Tohru Furuyama; Takashi Ohsawa; Yousei Nagahama; Hiroto Tanaka; Yohji Watanabe; Tohru Kimura; Kazuyoshi Muraoka; Kenji Natori (IEEE J. Solid State Circuits, 1989)

A 12 MHz data cycle 4 Mb DRAM with pipeline operation. - Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Yousei Nagahama; Tohru Furuyama (IEEE J. Solid State Circuits, 1991)