A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%. - Yuji Yokoyama; Nybutaka Itoh; Masap Katayama; Kazumasa Takashima; Hiroshi Akasaki; Masayuki Kaneda; Toshitsugu Ueda; Yousuke Tanaka; Eiji Yamasaki; Masaya Todokoro; Keinosuke Toriyama; Hiroshi Miki; et al. (CICC, 2000)

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. - Yuji Yokoyama; Nobutaka Itoh; Masatoshi Hasegawa; Masahiro Katayama; Hiroshi Akasaki; Masayuki Kaneda; Toshitsugu Ueda; Yousuke Tanaka; Eiji Yamasaki; Masaya Todokoro; Keinosuke Toriyama; Hiroshi Miki; et al. (IEEE J. Solid State Circuits, 2001)