HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies. - Ruifan Xu; Youwei Xiao; Jin Luo; Yun Liang 001 (ICCAD, 2022)

Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis. - Youwei Xiao; Zizhang Luo; Kexing Zhou; Yun Liang 001 (FPGA, 2024)

OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection. - Fan Cui; Chenyang Yin; Kexing Zhou; Youwei Xiao; Guangyu Sun 003; Qiang Xu 001; Qipeng Guo; Yun Liang 001; Xingcheng Zhang; Demin Song; Dahua Lin (ICCAD, 2024)

OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection. - Fan Cui; Chenyang Yin; Kexing Zhou; Youwei Xiao; Guangyu Sun 003; Qiang Xu 001; Qipeng Guo; Demin Song; Dahua Lin; Xingcheng Zhang; Yun Liang 001 (CoRR, 2024)

An Empirical Comparision of LLM-based Hardware Design and High-level Synthesis. - Fan Cui; Youwei Xiao; Kexing Zhou; Yun Liang 001 (FPGA, 2025)