A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier. - Chunyu Peng; Youwu Tao; Wenjuan Lu; Zhengping Li; Xinchun Ji; Jinlong Yan; Junning Chen (IEICE Electron. Express, 2015)

Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]. - Chunyu Peng; Youwu Tao; Wenjuan Lu; Zhengping Li; Xinchun Ji; Jinlong Yan; Junning Chen (IEICE Electron. Express, 2015)

Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier. - Shoubiao Tan; Wenjuan Lu; Chunyu Peng; Zhengping Li; Youwu Tao; Junning Chen (Frontiers Inf. Technol. Electron. Eng., 2015)

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier. - Zhengping Li; Chunyu Peng; Wenjuan Lu; Lijun Guan; Youwu Tao; Xincun Ji; Junning Chen (IEICE Electron. Express, 2016)