The VLSI Architecture and Implementation of a Low Complexity and Highly Efficient Configurable SVD Processor for MIMO Communication Systems. - Wei-Jhe Chen; Yu-An Lai; Chung-An Shen (Circuits Syst. Signal Process., 2020)

Design of 2D Systolic Array Accelerator for Quantized Convolutional Neural Networks. - Chia-Ning Liu; Yu-An Lai; Chih-Hung Kuo; Shi-An Zhan (VLSI-DAT, 2021)

The Design and Implementation of a Highly Efficient and Low-Complexity Joint-MMSE GFDM Receiver. - Yu-An Lai; Chung-An Shen (J. Signal Process. Syst., 2021)