Design considerations for variable-rate digital signal processing. - Yu Chen 013; Yannis P. Tsividis (ISCAS, 2016)

Signal processing in continuous time using asynchronous techniques. - Yu Chen 013; Yannis P. Tsividis (ACSSC, 2017)

Design of tunable digital delay cells. - Yu Chen 013; Rajit Manohar; Yannis P. Tsividis (CICC, 2017)

A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption. - Yu Chen 013; Xiaoyang Zhang; Yong Lian 001; Rajit Manohar; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2018)

Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays. - Sharvil Patil; Suhas Gundu Rao; Yu Chen 013; Yannis P. Tsividis (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)